| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| D | fp_cvt_int.d | 9 4: 9e2000e7 fcvtns x7, s7
11 c: 9e2100e7 fcvtnu x7, s7
13 14: 9e2800e7 fcvtps x7, s7
15 1c: 9e2900e7 fcvtpu x7, s7
17 24: 9e3000e7 fcvtms x7, s7
19 2c: 9e3100e7 fcvtmu x7, s7
21 34: 9e3800e7 fcvtzs x7, s7
23 3c: 9e3900e7 fcvtzu x7, s7
25 44: 9e2200e7 scvtf s7, x7
27 4c: 9e2300e7 ucvtf s7, x7
[all …]
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| D | ldst-exclusive.d | 8 0: 080f7ce1 stxrb w15, w1, \[x7\]
9 4: 080f7ce1 stxrb w15, w1, \[x7\]
10 8: 080f7ce1 stxrb w15, w1, \[x7\]
11 c: 480f7ce1 stxrh w15, w1, \[x7\]
12 10: 480f7ce1 stxrh w15, w1, \[x7\]
13 14: 480f7ce1 stxrh w15, w1, \[x7\]
14 18: 880f7ce1 stxr w15, w1, \[x7\]
15 1c: 880f7ce1 stxr w15, w1, \[x7\]
16 20: 880f7ce1 stxr w15, w1, \[x7\]
17 24: c80f7ce1 stxr w15, x1, \[x7\]
[all …]
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| D | virthostext.d | 12 [0-9a-f]+: d51d4007 msr spsr_el12, x7
13 [0-9a-f]+: d53d4007 mrs x7, spsr_el12
14 [0-9a-f]+: d51d4027 msr elr_el12, x7
15 [0-9a-f]+: d53d4027 mrs x7, elr_el12
16 [0-9a-f]+: d51d1007 msr sctlr_el12, x7
17 [0-9a-f]+: d53d1007 mrs x7, sctlr_el12
18 [0-9a-f]+: d51d1047 msr cpacr_el12, x7
19 [0-9a-f]+: d53d1047 mrs x7, cpacr_el12
20 [0-9a-f]+: d51c2027 msr ttbr1_el2, x7
21 [0-9a-f]+: d53c2027 mrs x7, ttbr1_el2
[all …]
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| D | virthostext-directive.d | 12 [0-9a-f]+: d51d4007 msr spsr_el12, x7
13 [0-9a-f]+: d53d4007 mrs x7, spsr_el12
14 [0-9a-f]+: d51d4027 msr elr_el12, x7
15 [0-9a-f]+: d53d4027 mrs x7, elr_el12
16 [0-9a-f]+: d51d1007 msr sctlr_el12, x7
17 [0-9a-f]+: d53d1007 mrs x7, sctlr_el12
18 [0-9a-f]+: d51d1047 msr cpacr_el12, x7
19 [0-9a-f]+: d53d1047 mrs x7, cpacr_el12
20 [0-9a-f]+: d51c2027 msr ttbr1_el2, x7
21 [0-9a-f]+: d53c2027 mrs x7, ttbr1_el2
[all …]
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| D | sysreg-1.s | 33 rw_sys_reg sys_reg=id_aa64afr0_el1 xreg=x7 r=1 w=0
34 rw_sys_reg sys_reg=id_aa64afr1_el1 xreg=x7 r=1 w=0
35 rw_sys_reg sys_reg=mvfr2_el1 xreg=x7 r=1 w=0
36 rw_sys_reg sys_reg=dlr_el0 xreg=x7 r=1 w=1
37 rw_sys_reg sys_reg=dspsr_el0 xreg=x7 r=1 w=1
39 rw_sys_reg sys_reg=sder32_el3 xreg=x7 r=1 w=1
40 rw_sys_reg sys_reg=mdcr_el3 xreg=x7 r=1 w=1
42 rw_sys_reg sys_reg=mdccint_el1 xreg=x7 r=1 w=1
44 rw_sys_reg sys_reg=dbgvcr32_el2 xreg=x7 r=1 w=1
46 rw_sys_reg sys_reg=fpexc32_el2 xreg=x7 r=1 w=1
[all …]
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| D | virthostext.s | 33 rw_sys_reg spsr_el12 x7
34 rw_sys_reg elr_el12 x7
36 rw_sys_reg sctlr_el12 x7
37 rw_sys_reg cpacr_el12 x7
39 rw_sys_reg ttbr1_el2 x7
40 rw_sys_reg ttbr0_el12 x7
41 rw_sys_reg ttbr1_el12 x7
43 rw_sys_reg tcr_el12 x7
45 rw_sys_reg afsr0_el12 x7
46 rw_sys_reg afsr1_el12 x7
[all …]
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| D | bitfield-no-aliases.d | 10 4: 93401cff sbfm xzr, x7, #0, #7
12 c: 93403cff sbfm xzr, x7, #0, #15
13 10: 93407cff sbfm xzr, x7, #0, #31
23 38: 9340fcff sbfm xzr, x7, #0, #63
24 3c: 935ffcff sbfm xzr, x7, #31, #63
25 40: 937ffcff sbfm xzr, x7, #63, #63
29 50: d340fcff ubfm xzr, x7, #0, #63
30 54: d35ffcff ubfm xzr, x7, #31, #63
31 58: d37ffcff ubfm xzr, x7, #63, #63
35 68: d340fcff ubfm xzr, x7, #0, #63
[all …]
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| D | neon-vfp-reglist-post.d | 72 100: 0cc77000 ld1 {v0.8b}, \[x0\], x7
73 104: 0cc7a000 ld1 {v0.8b, v1.8b}, \[x0\], x7
74 108: 0cc76000 ld1 {v0.8b-v2.8b}, \[x0\], x7
75 10c: 0cc72000 ld1 {v0.8b-v3.8b}, \[x0\], x7
76 110: 0cc77400 ld1 {v0.4h}, \[x0\], x7
77 114: 0cc7a400 ld1 {v0.4h, v1.4h}, \[x0\], x7
78 118: 0cc76400 ld1 {v0.4h-v2.4h}, \[x0\], x7
79 11c: 0cc72400 ld1 {v0.4h-v3.4h}, \[x0\], x7
80 120: 0cc77800 ld1 {v0.2s}, \[x0\], x7
81 124: 0cc7a800 ld1 {v0.2s, v1.2s}, \[x0\], x7
[all …]
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| D | bitfield-dump | 20 38: 9340fcff asr xzr, x7, #0
21 3c: 935ffcff asr xzr, x7, #31
22 40: 937ffcff asr xzr, x7, #63
26 50: d340fcff lsr xzr, x7, #0
27 54: d35ffcff lsr xzr, x7, #31
28 58: d37ffcff lsr xzr, x7, #63
32 68: d340fcff lsr xzr, x7, #0
33 6c: d36180ff lsl xzr, x7, #31
34 70: d34100ff lsl xzr, x7, #63
42 90: 934000ff sbfx xzr, x7, #0, #1
[all …]
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| D | ldst-exclusive.s | 26 \op w1, [x7]
27 \op w1, [x7, #0]
28 \op w1, [x7, 0]
33 \op x1, [x7]
34 \op x1, [x7, #0]
35 \op x1, [x7, 0]
40 \op w15, w1, [x7]
41 \op w15, w1, [x7, #0]
42 \op w15, w1, [x7, 0]
47 \op w15, x1, [x7]
[all …]
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| D | tlbi_op.d | 8 0: d50c8027 tlbi ipas2e1is, x7
9 4: d50c80a7 tlbi ipas2le1is, x7
13 14: d5088327 tlbi vae1is, x7
14 18: d50c8327 tlbi vae2is, x7
15 1c: d50e8327 tlbi vae3is, x7
16 20: d5088347 tlbi aside1is, x7
17 24: d5088367 tlbi vaae1is, x7
19 2c: d50883a7 tlbi vale1is, x7
20 30: d50c83a7 tlbi vale2is, x7
21 34: d50e83a7 tlbi vale3is, x7
[all …]
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| D | addsub.d | 116 1b0: 8b0100f0 add x16, x7, x1
117 1b4: 8b2100f0 add x16, x7, w1, uxtb
118 1b8: 8b2100f0 add x16, x7, w1, uxtb
119 1bc: 8b2104f0 add x16, x7, w1, uxtb #1
120 1c0: 8b2108f0 add x16, x7, w1, uxtb #2
121 1c4: 8b210cf0 add x16, x7, w1, uxtb #3
122 1c8: 8b2110f0 add x16, x7, w1, uxtb #4
123 1cc: 8b2120f0 add x16, x7, w1, uxth
124 1d0: 8b2120f0 add x16, x7, w1, uxth
125 1d4: 8b2124f0 add x16, x7, w1, uxth #1
[all …]
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| D | sysreg-2.d | 11 [0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
13 [0-9a-f]+: d5185327 msr errselr_el1, x7
14 [0-9a-f]+: d5385327 mrs x7, errselr_el1
35 [0-9a-f]+: d5189a07 msr pmblimitr_el1, x7
36 [0-9a-f]+: d5389a07 mrs x7, pmblimitr_el1
37 [0-9a-f]+: d5189a27 msr pmbptr_el1, x7
38 [0-9a-f]+: d5389a27 mrs x7, pmbptr_el1
39 [0-9a-f]+: d5189a67 msr pmbsr_el1, x7
40 [0-9a-f]+: d5389a67 mrs x7, pmbsr_el1
41 [0-9a-f]+: d5189ae7 msr pmbidr_el1, x7
[all …]
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| D | ldst-reg-reg-offset.d | 18 28: 3c276be7 str b7, \[sp,x7\]
19 2c: 3c277be7 str b7, \[sp,x7,lsl #0\]
20 30: 7c276be7 str h7, \[sp,x7\]
21 34: 7c277be7 str h7, \[sp,x7,lsl #1\]
22 38: bc276be7 str s7, \[sp,x7\]
23 3c: bc277be7 str s7, \[sp,x7,lsl #2\]
24 40: fc276be7 str d7, \[sp,x7\]
25 44: fc277be7 str d7, \[sp,x7,lsl #3\]
26 48: 3ca76be7 str q7, \[sp,x7\]
27 4c: 3ca77be7 str q7, \[sp,x7,lsl #4\]
[all …]
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| D | ldst-reg-unscaled-imm.d | 138 208: f81003e7 stur x7, \[sp,#-256\]
139 20c: f81553e7 stur x7, \[sp,#-171\]
140 210: f80003e7 stur x7, \[sp\]
141 214: f80003e7 stur x7, \[sp\]
142 218: f80023e7 stur x7, \[sp,#2\]
143 21c: f80043e7 stur x7, \[sp,#4\]
144 220: f80083e7 stur x7, \[sp,#8\]
145 224: f80103e7 stur x7, \[sp,#16\]
146 228: f80553e7 stur x7, \[sp,#85\]
147 22c: f80ff3e7 stur x7, \[sp,#255\]
[all …]
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| D | ldst-reg-pair.d | 20 30: 69603fe7 ldpsw x7, x15, \[sp,#-256\]
21 34: 6970bfe7 ldpsw x7, x15, \[sp,#-124\]
22 38: 697fbfe7 ldpsw x7, x15, \[sp,#-4\]
23 3c: 69403fe7 ldpsw x7, x15, \[sp\]
24 40: 6947bfe7 ldpsw x7, x15, \[sp,#60\]
25 44: 695fbfe7 ldpsw x7, x15, \[sp,#252\]
26 48: a9203fe7 stp x7, x15, \[sp,#-512\]
27 4c: a930bfe7 stp x7, x15, \[sp,#-248\]
28 50: a93fbfe7 stp x7, x15, \[sp,#-8\]
29 54: a9003fe7 stp x7, x15, \[sp\]
[all …]
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| D | ldst-reg-uns-imm.d | 151 23c: f81003e7 stur x7, \[sp,#-256\]
152 240: f81553e7 stur x7, \[sp,#-171\]
153 244: f90003e7 str x7, \[sp\]
154 248: f90003e7 str x7, \[sp\]
155 24c: f80023e7 stur x7, \[sp,#2\]
156 250: f80043e7 stur x7, \[sp,#4\]
157 254: f90007e7 str x7, \[sp,#8\]
158 258: f9000be7 str x7, \[sp,#16\]
159 25c: f80553e7 stur x7, \[sp,#85\]
160 260: f80ff3e7 stur x7, \[sp,#255\]
[all …]
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| D | ldst-reg-imm-post-ind.d | 125 1d4: f81007e7 str x7, \[sp\],#-256
126 1d8: f81557e7 str x7, \[sp\],#-171
127 1dc: f80007e7 str x7, \[sp\],#0
128 1e0: f80027e7 str x7, \[sp\],#2
129 1e4: f80047e7 str x7, \[sp\],#4
130 1e8: f80087e7 str x7, \[sp\],#8
131 1ec: f80107e7 str x7, \[sp\],#16
132 1f0: f80557e7 str x7, \[sp\],#85
133 1f4: f80ff7e7 str x7, \[sp\],#255
161 264: f85007e7 ldr x7, \[sp\],#-256
[all …]
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| D | ldst-reg-imm-pre-ind.d | 125 1d4: f8100fe7 str x7, \[sp,#-256\]!
126 1d8: f8155fe7 str x7, \[sp,#-171\]!
127 1dc: f8000fe7 str x7, \[sp,#0\]!
128 1e0: f8002fe7 str x7, \[sp,#2\]!
129 1e4: f8004fe7 str x7, \[sp,#4\]!
130 1e8: f8008fe7 str x7, \[sp,#8\]!
131 1ec: f8010fe7 str x7, \[sp,#16\]!
132 1f0: f8055fe7 str x7, \[sp,#85\]!
133 1f4: f80fffe7 str x7, \[sp,#255\]!
161 264: f8500fe7 ldr x7, \[sp,#-256\]!
[all …]
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| D | illegal.l | 42 [^:]*:72: Error: .*`sttr x7,\[x15,#1\]!'
118 [^:]*:169: Error: .*`sysl x7,#10,C15,C7,#11'
172 [^:]*:264: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
176 [^:]*:264: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
180 [^:]*:264: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
184 [^:]*:264: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
188 [^:]*:264: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
192 [^:]*:264: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
196 [^:]*:270: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
200 [^:]*:270: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
[all …]
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| D | system.d | 143 21c: d52bf7e7 sysl x7, #3, C15, C7, #7
196 2ec: f8be58e0 prfm pldl1keep, \[x7,w30,uxtw #3\]
201 2fc: f8be58e1 prfm pldl1strm, \[x7,w30,uxtw #3\]
206 30c: f8be58e2 prfm pldl2keep, \[x7,w30,uxtw #3\]
211 31c: f8be58e3 prfm pldl2strm, \[x7,w30,uxtw #3\]
216 32c: f8be58e4 prfm pldl3keep, \[x7,w30,uxtw #3\]
221 33c: f8be58e5 prfm pldl3strm, \[x7,w30,uxtw #3\]
226 34c: f8be58e6 prfm #0x06, \[x7,w30,uxtw #3\]
231 35c: f8be58e7 prfm #0x07, \[x7,w30,uxtw #3\]
236 36c: f8be58e8 prfm plil1keep, \[x7,w30,uxtw #3\]
[all …]
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| D | sysreg-2.s | 15 rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
20 rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
48 rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
52 rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
56 rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
60 rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=0
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| D | armv8-ras-1.d | 12 [^:]+: d5185327 msr errselr_el1, x7
13 [^:]+: d5385327 mrs x7, errselr_el1
32 [^:]+: d5185327 msr errselr_el1, x7
33 [^:]+: d5385327 mrs x7, errselr_el1
52 [^:]+: d5185327 msr errselr_el1, x7
53 [^:]+: d5385327 mrs x7, errselr_el1
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| D | pr19721.s | 3 mov x7, x17
4 mov x7, x17, lsl 25
5 orr x7, xzr, x17, lsl 25
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| D | pr19721.d | 8 0: aa1103e7 mov x7, x17
9 4: aa1167e7 mov x7, x17, lsl #25
10 8: aa1167e7 mov x7, x17, lsl #25
|