Searched refs:RegClassID (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
165 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
186 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
188 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
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| D | AMDGPUDisassembler.h | 44 const char* getRegClassName(unsigned RegClassID) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 506 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
507 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
510 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 289 unsigned RegClassID; in Select() local
296 RegClassID = selectSGPRVectorRegClassID(NumVectorElts); in Select()
303 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break; in Select()
306 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID; in Select()
308 RegClassID = AMDGPU::R600_Reg128RegClassID; in Select()
315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
330 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 686 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1026 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1028 switch (RegClassID) { in GetSIDIForRegClass()
1062 int RegClassID = -1; in VerifyAndAdjustOperands() local
1083 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1084 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1090 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1092 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1094 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1101 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1559 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1567 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); in DecodeGPRSeqPairsClassRegisterClass()
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