Searched refs:SrcHi (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
581 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1279 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo() local
1283 .addReg(SrcHi) in expandPostRAPseudo()
1286 SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo()
1290 .addReg(SrcHi) in expandPostRAPseudo()
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| D | HexagonFrameLowering.cpp | 1551 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); in expandStoreVec2() local
1586 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX86BaseImpl.h | 6723 Operand *SrcHi = hiOperand(Src);
6729 _mov(T_Hi, SrcHi);
7241 Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm);
7250 _adc_rmw(AddrHi, SrcHi);
7254 _sbb_rmw(AddrHi, SrcHi);
7258 _and_rmw(AddrHi, SrcHi);
7262 _or_rmw(AddrHi, SrcHi);
7266 _xor_rmw(AddrHi, SrcHi);
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| D | IceInstARM32.cpp | 1932 auto *SrcHi = llvm::cast<Variable>(getSrc(1)); in emitSingleDestMultiSource() local
1934 assert(SrcHi->hasReg()); in emitSingleDestMultiSource()
1945 SrcHi->emit(Func); in emitSingleDestMultiSource()
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| D | IceTargetLoweringARM32.h | 321 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
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| D | IceTargetLoweringARM32.cpp | 2289 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check() argument
2290 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) in div0Check()
2310 _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex)); in div0Check()
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