| /external/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local
183 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findComponents()
225 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local
226 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in rewriteOperands()
336 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
337 if (SubRegIdx == 0) in computeMainRangesFixFlags()
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| D | RegisterPressure.cpp | 492 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local
495 pushRegLanes(Reg, SubRegIdx, RegOpers.Uses); in collectOperandLanes()
500 SubRegIdx = 0; in collectOperandLanes()
504 pushRegLanes(Reg, SubRegIdx, RegOpers.DeadDefs); in collectOperandLanes()
506 pushRegLanes(Reg, SubRegIdx, RegOpers.Defs); in collectOperandLanes()
510 void pushRegLanes(unsigned Reg, unsigned SubRegIdx, in pushRegLanes() argument
513 LaneBitmask LaneMask = SubRegIdx != 0 in pushRegLanes()
514 ? TRI.getSubRegIndexLaneMask(SubRegIdx) in pushRegLanes()
1192 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
1193 LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx); in findUseBetween()
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| D | StackMaps.cpp | 145 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
146 if (SubRegIdx) in parseOperand()
147 Offset = TRI->getSubRegIdxOffset(SubRegIdx); in parseOperand()
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| D | VirtRegMap.cpp | 340 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
341 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx); in readsUndefSubreg()
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| D | MachineVerifier.cpp | 1224 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1225 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1226 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
1325 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
1326 LaneBitmask MOMask = SubRegIdx != 0 in checkLiveness()
1327 ? TRI->getSubRegIndexLaneMask(SubRegIdx) in checkLiveness()
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| D | RegisterCoalescer.cpp | 214 MachineOperand &MO, unsigned SubRegIdx);
1217 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() argument
1218 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); in addUndefFlag()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 655 unsigned SubRegIdx = (is32Bit ? in Select() local
660 CurDAG->getTargetConstant(SubRegIdx, in Select()
669 unsigned SubRegIdx = (is32Bit ? in Select() local
674 CurDAG->getTargetConstant(SubRegIdx, in Select()
715 unsigned SubRegIdx = (is32Bit ? in Select() local
720 CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); in Select()
740 unsigned SubRegIdx = (is32Bit ? in Select() local
745 CurDAG->getTargetConstant(SubRegIdx, in Select()
753 unsigned SubRegIdx = (is32Bit ? in Select() local
758 CurDAG->getTargetConstant(SubRegIdx, in Select()
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
196 if (SubRegIdx == X86::sub_8bit_hi) in getSuperRegDestIfDead()
202 if (SubRegIdx == X86::sub_8bit) { in getSuperRegDestIfDead()
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| D | X86InstrAVX512.td | 116 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
4067 _.RC:$src1, _.SubRegIdx),
4069 _.RC:$src2, _.SubRegIdx)),
6890 _.RC:$src, _.SubRegIdx)),
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 1102 unsigned SubRegIdx = 0);
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 155 unsigned SubRegIdx);
157 unsigned SubRegIdx);
1135 unsigned SubRegIdx) { in SelectLoad() argument
1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1156 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad() argument
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
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| D | AArch64InstrInfo.td | 2077 SubRegIndex SubRegIdx,
2082 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2087 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 212 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); in getOperandRegClass() local
214 SubRegIdx); in getOperandRegClass()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 3440 SDValue SubRegIdx = in Select() local
3443 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); in Select()
3453 SDValue SubRegIdx = in Select() local
3456 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx); in Select()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3227 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX() local
3284 .addReg(LaneReg, 0, SubRegIdx); in emitINSERT_DF_VIDX()
3313 .addReg(LaneTmp2, 0, SubRegIdx); in emitINSERT_DF_VIDX()
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