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Searched refs:addc (Results 1 – 25 of 72) sorted by relevance

123

/external/antlr/antlr-3.4/runtime/C/src/
Dantlr3debughandlers.c406 buffer->addc(buffer, character); in serializeText()
439 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeToken()
441 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeToken()
443 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeToken()
445 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeToken()
494 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeNode()
499 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeNode()
509 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeNode()
515 delboy->tokenString->addc(delboy->tokenString, ' '); in serializeNode()
523 delboy->tokenString->addc(delboy->tokenString, '\t'); in serializeNode()
[all …]
Dantlr3basetreeadaptor.c223 dotSpec->addc(dotSpec, text->charAt(text, j)); in defineDotNodes()
310 dotSpec->addc(dotSpec, text->charAt(text, j)); in defineDotEdges()
339 dotSpec->addc(dotSpec, text->charAt(text, j)); in defineDotEdges()
416 dotSpec->addc(dotSpec, text->charAt(text, j)); in makeDot()
Dantlr3commontreenodestream.c846 text->addc (text, ' '); in toStringWork()
862 buf->addc (buf, ' '); in toStringWork()
876 buf->addc (buf, ' '); in toStringWork()
/external/llvm/test/CodeGen/SystemZ/
Dargs-06.ll16 %addc = add i8 %addb, %c
17 %addd = add i8 %addc, %d
34 %addc = add i16 %addb, %c
35 %addd = add i16 %addc, %d
52 %addc = add i32 %addb, %c
53 %addd = add i32 %addc, %d
70 %addc = add i64 %addb, %c
71 %addd = add i64 %addc, %d
/external/llvm/test/MC/Lanai/
Dv11.s19 addc %r17, %r18, %r21 label
21 addc.f %r17, %r18, %r21
23 addc %r17, 0, %r21 label
25 addc %r17, 0x00001234, %r21 label
27 addc %r17, 0x12340000, %r21 label
29 addc.f %r17, 0, %r21
31 addc.f %r17, 0x00001234, %r21
33 addc.f %r17, 0x12340000, %r21
335 ld [%r17 addc %r18], %r21
353 ld [*%r17 addc %r18], %r21
[all …]
/external/valgrind/none/tests/ppc64/
Djm-int.stdout.exp-LE-ISA3_022 addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
23 addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
24 addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
25 addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
26 addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
27 addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
28 addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
29 addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
30 addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
251 addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
[all …]
Djm-int.stdout.exp22 addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
23 addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
24 addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
25 addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
26 addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
27 addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
28 addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
29 addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
30 addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
/external/llvm/test/MC/Disassembler/Lanai/
Dv11.txt20 # CHECK: addc %r17, %r18, %r21
22 # CHECK: addc.f %r17, %r18, %r21
24 # CHECK: addc %r17, 0x0, %r21
26 # CHECK: addc %r17, 0x1234, %r21
28 # CHECK: addc %r17, 0x12340000, %r21
30 # CHECK: addc.f %r17, 0x0, %r21
32 # CHECK: addc.f %r17, 0x1234, %r21
34 # CHECK: addc.f %r17, 0x12340000, %r21
282 # CHECK: ld [%r17 addc %r18], %r21
300 # CHECK: ld [*%r17 addc %r18], %r21
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td433 "addc.b\t{$src2, $dst}",
438 "addc.w\t{$src2, $dst}",
445 "addc.b\t{$src2, $dst}",
450 "addc.w\t{$src2, $dst}",
456 "addc.b\t{$src2, $dst}",
461 "addc.w\t{$src2, $dst}",
468 "addc.b\t{$src, $dst}",
473 "addc.w\t{$src, $dst}",
479 "addc.b\t{$src, $dst}",
484 "addc.w\t{$src, $dst}",
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430InstrInfo.td433 "addc.b\t{$src2, $dst}",
438 "addc.w\t{$src2, $dst}",
445 "addc.b\t{$src2, $dst}",
450 "addc.w\t{$src2, $dst}",
456 "addc.b\t{$src2, $dst}",
461 "addc.w\t{$src2, $dst}",
468 "addc.b\t{$src, $dst}",
473 "addc.w\t{$src, $dst}",
479 "addc.b\t{$src, $dst}",
484 "addc.w\t{$src, $dst}",
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dppc64-i128-abi.ll123 ; Add the lower 64-bits using addc on registers 3 and 5
131 ; Add the lower 64-bits using addc on registers 4 and 6
138 ; CHECK-LE: addc 3, 3, 5
143 ; CHECK-BE: addc 4, 4, 6
148 ; CHECK-LE-NOVSX: addc 3, 3, 5
153 ; CHECK-BE-NOVSX: addc 4, 4, 6
Dbig-endian-actual-args.ll2 ; RUN: grep "addc 4, 4, 6"
Daddc.ll9 ; CHECK: addc r4, r6, r4
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding.s.cs77 0x7c,0x43,0x20,0x14 = addc 2, 3, 4
78 0x7c,0x43,0x20,0x15 = addc. 2, 3, 4
/external/swiftshader/third_party/LLVM/test/MC/MBlaze/
Dmblaze_typea.s14 # CHECK: addc
17 addc r1, r2, r3
/external/valgrind/none/tests/ppc32/
Djm-int.stdout.exp22 addc 00000000, 00000000 => 00000000 (00000000 00000000)
23 addc 00000000, 000f423f => 000f423f (00000000 00000000)
24 addc 00000000, ffffffff => ffffffff (00000000 00000000)
25 addc 000f423f, 00000000 => 000f423f (00000000 00000000)
26 addc 000f423f, 000f423f => 001e847e (00000000 00000000)
27 addc 000f423f, ffffffff => 000f423e (00000000 20000000)
28 addc ffffffff, 00000000 => ffffffff (00000000 00000000)
29 addc ffffffff, 000f423f => 000f423e (00000000 20000000)
30 addc ffffffff, ffffffff => fffffffe (00000000 20000000)
/external/llvm/test/CodeGen/AMDGPU/
Duaddo.ll10 ; SI: addc
11 ; SI: addc
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dbig-endian-actual-args.ll2 ; RUN: grep {addc 4, 4, 6}
Daddc.ll9 ; CHECK: addc r4, r6, r4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s321 # CHECK-BE: addc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x14]
322 # CHECK-LE: addc 2, 3, 4 # encoding: [0x14,0x20,0x43,0x7c]
323 addc 2, 3, 4
324 # CHECK-BE: addc. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x15]
325 # CHECK-LE: addc. 2, 3, 4 # encoding: [0x15,0x20,0x43,0x7c]
326 addc. 2, 3, 4
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/llvm/test/CodeGen/ARM/
D2011-08-29-SchedCycle.ll30 ; fix subc / sube (and addc / adde) to use physical register dependency instead.
/external/antlr/antlr-3.4/runtime/C/include/
Dantlr3string.h146 pANTLR3_UINT8 (*addc) (struct ANTLR3_STRING_struct * string, ANTLR3_UINT32 c); member
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/
Dmblaze_typea.txt10 # CHECK: addc r1, r2, r3
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td49 // `AAA' specifies the operation: `add' (000), `addc' (001), `sub'
71 // For arithmetic instructions (`add', `addc', `sub', `subb') `V' is
123 // `BBB' determines the operation: `add' (000), `addc' (001), `sub'
139 // Except for arithmetic instructions (`add', `addc', `sub', `subb'), `V'

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