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Searched refs:enableSubRegLiveness (Results 1 – 11 of 11) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h111 bool enableSubRegLiveness() const override;
DHexagonSubtarget.cpp131 bool HexagonSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in HexagonSubtarget
/external/llvm/include/llvm/Target/
DTargetSubtargetInfo.h206 virtual bool enableSubRegLiveness() const { return false; } in enableSubRegLiveness() function
/external/llvm/lib/Target/PowerPC/
DPPCSubtarget.cpp218 bool PPCSubtarget::enableSubRegLiveness() const { in enableSubRegLiveness() function in PPCSubtarget
DPPCSubtarget.h309 bool enableSubRegLiveness() const override;
/external/llvm/lib/Target/AMDGPU/
DAMDGPUSubtarget.h289 bool enableSubRegLiveness() const override { in enableSubRegLiveness() function
/external/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp362 if (!MF.getSubtarget().enableSubRegLiveness()) in runOnMachineFunction()
DDetectDeadLanes.cpp580 if (!MF.getSubtarget().enableSubRegLiveness()) { in runOnMachineFunction()
DLiveIntervalAnalysis.cpp122 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness()) in runOnMachineFunction()
123 MRI->enableSubRegLiveness(true); in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h202 void enableSubRegLiveness(bool Enable = true) {
/external/llvm/lib/CodeGen/MIRParser/
DMIRParser.cpp364 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness); in initializeRegisterInfo()