Searched refs:FL2 (Results 1 – 2 of 2) sorted by relevance
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| D | i960.h | 117 #define FL2 OP( 1, LIT, FP, 0 ) macro
354 { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } },
370 { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } },
371 { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } },
372 { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } },
373 { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } },
374 { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } },
375 { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } },
376 { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } },
377 { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } },
[all …]
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| /toolchain/binutils/binutils-2.27/opcodes/ |
| D | ppc-opc.c | 373 #define FL2 FL1 + 1 macro
377 #define FLM FL2 + 1
4189 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4191 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
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