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Searched refs:LDR (Results 1 – 25 of 25) sorted by relevance

/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
Dpr20068.s4 LDR R0, =0x12345678 label
5 @LDR R0, =0x87654321
Dgroup-reloc-ldr-parsing-bad.s1 @ Tests that are supposed to fail during parsing of LDR group relocations.
5 @ No NC variants exist for the LDR relocations.
Dgroup-reloc-ldr-encoding-bad.s2 @ for LDR group relocations.
24 @ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
Dgroup-reloc-ldr.s1 @ Tests for LDR group relocations.
23 @ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
Dpr18347.l2 [^:]*:2: Warning: \[-mwarn-syms\]: Assignment makes a symbol match an ARM instruction: LDR
Dpr18347.d1 # name: PR18347 - GAS silently ignores a misconstructed LDR instruction
Dpr18347.s2 LDR =garbage // no destination register
Dldr-global.d2 #name: PC-relative LDR from global
Dsp-pc-validations-bad-t.s26 @ LDR (register)
37 @ LDR (literal)
42 @ LDR (register)
225 @ldrt r0,[pc,#4] => LDR (literal)
Dsp-pc-validations-bad.s6 @ LDR (immediate, ARM)
7 @ LDR (literal)
10 @ LDR (register)
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/
Dregression.s101 LDR R63,[R0,#0x0] ;//Load Word
105 LDR R63,[R0,#0xc] ;//Load Word
122 LDR R63,[R0,R4] ;//Load Word
143 LDR R63,[R0],R4 ;//Load Word
/toolchain/binutils/binutils-2.27/ld/testsuite/ld-arm/
Dgroup-relocs-ldr-bad.d1 #name: LDR group relocations failure test
Dgroup-relocs-ldr-bad-2.d1 #name: LDR group relocations failure test
Dgroup-relocs-ldr-bad-2.s1 @ Test intended to fail for LDR group relocations.
Dgroup-relocs-ldr-bad.s1 @ Test intended to fail for LDR group relocations.
Dgroup-relocs.s43 @ LDR, PC-relative
54 @ LDR, SB-relative
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-aarch64.texi211 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
212 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
411 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
412 @item LDR =
418 already there) and a PC-relative LDR instruction will be generated.
Dc-arm.texi1024 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1025 @item LDR
1031 instruction will be used in place of the LDR instruction, if the
1034 already there) and a PC relative LDR instruction will be generated.
/toolchain/binutils/binutils-2.27/gas/testsuite/
DChangeLog-2012127 * gas/aarch64/illegal.s: Add test for unaccepted LDR literal.
129 * gas/aarch64/programmer-friendly.s: Add tests for LDR literal with
DChangeLog-20151580 * gas/aarch64/diagnostic.s: Add LDR test.
/toolchain/binutils/binutils-2.27/opcodes/
DChangeLog-9899335 * arm-dis.c (print_insn_arm): Make LDRH/LDRB consistent with LDR
DChangeLog-0001654 * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR.
/toolchain/binutils/binutils-2.27/ld/testsuite/
DChangeLog-20141066 to include all 5 bits of LDR destination register.
/toolchain/binutils/binutils-2.27/gas/
DChangeLog-20151115 * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
DChangeLog-98991964 and LDR reg,=<expr> instruction.