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Searched refs:M1 (Results 1 – 25 of 34) sorted by relevance

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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/tic6x/
Dinsns-bad-1.s49 add .M1 a0,a0,a0
114 mvk .M1 0,a1
173 addsub .M1 a2,a3,a5:a4
177 addsub2 .M1 a2,a3,a5:a4
185 add2 .M1 a1,a2,a3
201 andn .M1 a1,a2,a3
206 avg2 .M1 a1,a2
207 avg2 .M1 b1,a2,a2
210 avgu4 .M1 a1,a2
211 avgu4 .M1 b1,a2,a2
[all …]
Dinsns16-m-unit.d10 [0-9a-f]+[02468ace] <[^>]*> 231e[ \t]+mpy \.M1 a1,a6,a0
14 [0-9a-f]+[02468ace] <[^>]*> a71e[ \t]+mpy \.M1 a5,a6,a2
17 [0-9a-f]+[02468ace] <[^>]*> 213e[ \t]+mpyh \.M1 a1,a2,a0
21 [0-9a-f]+[02468ace] <[^>]*> a53e[ \t]+mpyh \.M1 a5,a2,a2
25 [0-9a-f]+[02468ace] <[^>]*> 225e[ \t]+mpylh \.M1 a17,a20,a16
29 [0-9a-f]+[02468ace] <[^>]*> a6de[ \t]+mpylh \.M1 a21,a21,a18
32 [0-9a-f]+[02468ace] <[^>]*> 207e[ \t]+mpyhl \.M1 a17,a16,a16
36 [0-9a-f]+[02468ace] <[^>]*> a47e[ \t]+mpyhl \.M1 a21,a16,a18
40 [0-9a-f]+[02468ace] <[^>]*> 231e[ \t]+smpy \.M1 a17,a22,a16
44 [0-9a-f]+[02468ace] <[^>]*> a71e[ \t]+smpy \.M1 a21,a22,a18
[all …]
Dpredicate-bad-3.s13 [!a2] cmpy .M1 a1,a2,a5:a4
14 [!b2] cmpyr .M1 a1,a2,a5
15 [!a1] cmpyr1 .M1 a1,a2,a5
24 [b1] gmpy .M1 a1,a2,a3
26 [b2] mpy2ir .M1 a1,a2,a5:a4
32 [b1] smpy32 .M1 a0,a0,a0
35 [b0] xormpy .M1 a0,a1,a2
Dinsns-c674x-sploop.s16 spmask M1
20 spmask L1,S1,D1,M1,M2,D2,S2,L2
21 spmask M1
32 spmaskr M1
36 spmaskr L1,S1,D1,M1,M2,D2,S2,L2
37 spmaskr M1
Dinsns-c674x.s169 avg2 .M1 a8,a11,a14
173 avgu4 .M1 a8,a11,a14
194 bitc4 .M1 a4,a14
198 bitr .M1 a4,a14
354 cmpy .M1 a1,a2,a5:a4
358 cmpyr .M1 a1,a2,a5
362 cmpyr1 .M1 a1,a2,a5
366 ddotp4 .M1 a1,a2,a5:a4
370 ddotph2 .M1 a1:a0,a2,a5:a4
374 ddotph2r .M1 a1:a0,a2,a5
[all …]
Dinsns-c674x-sploop.d16 [0-9a-f]+[048c] <[^>]*> 01030000[ \t]+spmask M1
20 [0-9a-f]+[048c] <[^>]*> 03ff0000[ \t]+spmask L1,L2,S1,S2,D1,D2,M1,M2
21 [0-9a-f]+[048c] <[^>]*> 01170001[ \t]+spmask L1,S1,M1
32 [0-9a-f]+[048c] <[^>]*> 01032000[ \t]+spmaskr M1
36 [0-9a-f]+[048c] <[^>]*> 03ff2000[ \t]+spmaskr L1,L2,S1,S2,D1,D2,M1,M2
37 [0-9a-f]+[048c] <[^>]*> 01172001[ \t]+spmaskr L1,S1,M1
Dsploop-bad-1.s21 spmask .M1
24 spmaskr .M1
Dinsns-c674x.d172 [0-9a-f]+[048c] <[^>]*> 072d04f0[ \t]+avg2 \.M1 a8,a11,a14
176 [0-9a-f]+[048c] <[^>]*> 072d04b0[ \t]+avgu4 \.M1 a8,a11,a14
197 [0-9a-f]+[048c] <[^>]*> 0713c0f0[ \t]+bitc4 \.M1 a4,a14
201 [0-9a-f]+[048c] <[^>]*> 0713e0f0[ \t]+bitr \.M1 a4,a14
357 [0-9a-f]+[048c] <[^>]*> 120822b0[ \t]+cmpy \.M1 a1,a2,a5:a4
361 [0-9a-f]+[048c] <[^>]*> 128822f0[ \t]+cmpyr \.M1 a1,a2,a5
365 [0-9a-f]+[048c] <[^>]*> 12882330[ \t]+cmpyr1 \.M1 a1,a2,a5
369 [0-9a-f]+[048c] <[^>]*> 12082630[ \t]+ddotp4 \.M1 a1,a2,a5:a4
373 [0-9a-f]+[048c] <[^>]*> 120805f0[ \t]+ddotph2 \.M1 a1:a0,a2,a5:a4
377 [0-9a-f]+[048c] <[^>]*> 12880570[ \t]+ddotph2r \.M1 a1:a0,a2,a5
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/frv/
Dfr450-media-issue.s2 mand.p fr0,fr1,fr2 ; M1
3 mpackh fr4,fr5,fr6 ; M1 -- ok
4 mand.p fr0,fr1,fr2 ; M1
6 mand.p fr0,fr1,fr2 ; M1
8 mand.p fr0,fr1,fr2 ; M1
10 mand.p fr0,fr1,fr2 ; M1
12 mand.p fr0,fr1,fr2 ; M1
17 mpackh fr4,fr5,fr6 ; M1 -- error
31 mpackh fr4,fr5,fr6 ; M1 -- ok
45 mpackh fr4,fr5,fr6 ; M1 -- error
[all …]
/toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/
Dparallel.d14 18: 0a ce 10 04 R2 = EXTRACT \(R0, R2.L\) \(Z\) \|\| I3 \+= M1 \|\| NOP;
16 20: 0a ce 23 4e R7 = EXTRACT \(R3, R4.L\) \(X\) \|\| I3 \+= M1 \(BREV\) \|\| NOP;
58 c8: 25 cc 3e 0e R7.H = R7 \+ R6 \(RND12\) \|\| R1 = B\[P0\] \(X\) \|\| \[I3 \+\+ M1\] = R6;
122 1c8: 03 c8 21 0c A0 \+= R4.H \* R1.L \|\| R5 = B\[P2\] \(Z\) \|\| \[I1 \+\+ M1\] = R7;
124 1d0: 03 c9 3e 12 A0 -= R7.L \* R6.H \(IS\) \|\| R5 = B\[P3\] \(X\) \|\| \[I1 \+\+ M1\] = R6;
126 1d8: 03 c8 2a 16 A0 -= R5.H \* R2.H \|\| R5 = B\[P4\] \(Z\) \|\| \[I1 \+\+ M1\] = R5;
128 1e0: 10 c8 08 58 A1 = R1.L \* R0.H \(M\) \|\| R5 = B\[P5\] \(X\) \|\| \[I1 \+\+ M1\] = R4;
130 1e8: 00 c8 10 98 A1 = R2.H \* R0.L \|\| R5 = B\[SP\] \(Z\) \|\| \[I1 \+\+ M1\] = R3;
132 1f0: 70 c8 3e 98 A1 = R7.H \* R6.L \(M, W32\) \|\| R5 = B\[FP\] \(X\) \|\| \[I1 \+\+ M1\] = R2;
134 1f8: 81 c8 1a 18 A1 \+= R3.L \* R2.L \(FU\) \|\| R0.L = W\[I0\] \|\| \[I1 \+\+ M1\] = R1;
[all …]
Dstack2.s21 [--SP ] = M1;
78 M1= [ SP ++ ] ;
Dstack2.d15 e: 55 01 \[--SP\] = M1;
51 56: 15 01 M1 = \[SP\+\+\];
Dmove2.s79 R5 = M1;
97 P5 = M1;
117 A0.W = M1;
142 M1 = P0; define
146 M1 = A0.W; define
177 M1 = M0; define
Dparallel2.d32 60: 0a cc 3f 00 R0.L = A0.X \|\| R1 = \[I0 \+\+ M1\] \|\| NOP;
42 88: 29 cc 28 80 A1.H = R5.H \|\| R0 = \[I1 \+\+ M1\] \|\| NOP;
48 a0: 07 c8 40 18 R1.H = A1 \|\| R0 = \[I2 \+\+ M1\] \|\| NOP;
56 c0: 87 c8 00 38 R0.H = A1, R0.L = A0 \(FU\) \|\| R5 = \[I3 \+\+ M1\] \|\| NOP;
Dmove2.d65 72: ad 30 R5 = M1;
81 92: ad 32 P5 = M1;
97 b2: 8d 38 A0.W = M1;
117 da: 68 34 M1 = P0;
121 e2: 29 35 M1 = A0.W;
145 112: ac 34 M1 = M0;
Dstack.d13 c: 55 01 \[--SP\] = M1;
Dpseudo.s28 DBG M1;
Dpseudo.d28 2a: 15 f8 DBG M1;
Dparallel.s7 r7 = ExtracT (r3, r4.L) (X) || I3 += M1 (breV);
78 A0 += r4.h * r1.L || r5 = b [p2] (z) || [I1++M1] = R7;
Darithmetic.d71 8e: 75 9e I1 -= M1;
/toolchain/binutils/binutils-2.27/include/opcode/
Di960.h51 #define M1 0x0800 macro
74 #define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */
76 #define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */
/toolchain/binutils/binutils-2.27/cpu/
Dfrv.opc293 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
328 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
360 /* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
393 /* FMLOW */ UNIT_FM01, /* Only F0,F1,M0,M1 units */
/toolchain/binutils/binutils-2.27/gas/doc/
Dc-s390.texi557 @item bcr M1,R2 @tab b<m>r R2
558 @item bc M1,D2(X2,B2) @tab b<m> D2(X2,B2)
559 @item brc M1,I2 @tab j<m> I2
560 @item brcl M1,I2 @tab jg<m> I2
Dc-bfin.texi219 The set of 32-bit registers (M0, M1, M2, M3) that normally contain
/toolchain/binutils/binutils-2.27/opcodes/
Dmips-opc.c312 #define M1 INSN_10000 macro
1363 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 },
1364 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC, 0, M1|N5|EE, 0, 0 },
1478 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 },
1479 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, RD_1|WR_C0|CM, 0, M1|N5|EE, 0, 0 },

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