/toolchain/binutils/binutils-2.27/gas/testsuite/gas/ia64/ |
D | opc-a.d | 94 1c0: 00 10 0c 08 03 30 \[MII\] cmp\.lt p2,p3=r3,r4 95 1c6: 20 18 10 06 62 60 cmp\.lt p2,p3=3,r4 96 1cc: 40 18 08 c0 cmp\.lt p3,p2=r4,r3 97 1d0: 00 10 08 08 03 31 \[MII\] cmp\.lt p2,p3=2,r4 98 1d6: 20 20 0c 06 60 60 cmp\.lt p2,p3=r4,r3 99 1dc: 20 20 08 c4 cmp\.lt p3,p2=2,r4 100 1e0: 00 18 0c 08 02 30 \[MII\] cmp\.lt p3,p2=r3,r4 101 1e6: 30 18 10 04 62 40 cmp\.lt p3,p2=3,r4 114 22c: 38 20 0c c0 cmp\.lt\.unc p2,p3=r3,r4 115 230: 00 10 0e 08 03 31 \[MII\] cmp\.lt\.unc p2,p3=3,r4 [all …]
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D | opc-a.s | 108 cmp.lt p2, p3 = r3, r4 109 cmp.lt p2, p3 = 3, r4 129 cmp.lt.unc p2, p3 = r3, r4 130 cmp.lt.unc p2, p3 = 3, r4 198 cmp.lt.and p2, p3 = r0, r4 199 cmp.lt.and p2, p3 = r4, r0 200 cmp.lt.or p2, p3 = r0, r4 201 cmp.lt.or p2, p3 = r4, r0 202 cmp.lt.or.andcm p2, p3 = r0, r4 203 cmp.lt.or.andcm p2, p3 = r4, r0 [all …]
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D | opc-a-err.s | 23 cmp4.lt.or p2, p3 = r1, r4 24 cmp4.lt.or p2, p3 = 1, r4
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D | opc-f.d | 503 a46: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=f4,f5 506 a56: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=f4,f5 509 a66: 30 20 14 08 25 00 fcmp\.lt\.s1 p3,p4=f4,f5 512 a76: 30 20 14 08 26 00 fcmp\.lt\.s2 p3,p4=f4,f5 515 a86: 30 20 14 08 27 00 fcmp\.lt\.s3 p3,p4=f4,f5 518 a96: 30 24 14 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=f4,f5 521 aa6: 30 24 14 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=f4,f5 524 ab6: 30 24 14 08 25 00 fcmp\.lt\.unc\.s1 p3,p4=f4,f5 527 ac6: 30 24 14 08 26 00 fcmp\.lt\.unc\.s2 p3,p4=f4,f5 530 ad6: 30 24 14 08 27 00 fcmp\.lt\.unc\.s3 p3,p4=f4,f5 [all …]
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D | opc-f.s | 202 fcmp.lt p3, p4 = f4, f5 203 fcmp.lt.s0 p3, p4 = f4, f5 204 fcmp.lt.s1 p3, p4 = f4, f5 205 fcmp.lt.s2 p3, p4 = f4, f5 206 fcmp.lt.s3 p3, p4 = f4, f5 207 fcmp.lt.unc p3, p4 = f4, f5 208 fcmp.lt.unc.s0 p3, p4 = f4, f5 209 fcmp.lt.unc.s1 p3, p4 = f4, f5 210 fcmp.lt.unc.s2 p3, p4 = f4, f5 211 fcmp.lt.unc.s3 p3, p4 = f4, f5 [all …]
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
D | armv8-2-fp16-scalar-bad.s | 3 .irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16 11 .irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16 19 .irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16 27 .irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16 34 .irp cond, eq, ne, ge, lt, gt, le 42 .irp cond, eq, ne, ge, lt, gt, le 50 .irp cond, eq, ne, ge, lt, gt, le 59 .irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
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D | thumb2_bcond.s | 13 it lt 19 it lt
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D | thumb2_bcond.d | 13 0+0.. <[^>]+> bfb8[ ]+it lt 19 0+0.. <[^>]+> bfb8[ ]+it lt
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D | arm-it-auto.d | 34 00000040 <main\+0x40> bfb8 it lt 76 0000009a <main\+0x9a> bfb8 it lt 79 000000a0 <main\+0xa0> bfb8 it lt
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/ |
D | vle.d | 35 5c: 7f a3 02 02 e_crand 4\*cr7\+gt,so,lt 36 60: 7c 02 e9 02 e_crandc lt,eq,4\*cr7\+gt 37 64: 7d f0 8a 42 e_creqv 4\*cr3\+so,4\*cr4\+lt,4\*cr4\+gt 38 68: 7d e0 19 c2 e_crnand 4\*cr3\+so,lt,so 39 6c: 7d e0 18 42 e_crnor 4\*cr3\+so,lt,so 40 70: 7d 8d 73 82 e_cror 4\*cr3\+lt,4\*cr3\+gt,4\*cr3\+eq 42 78: 7c 00 01 82 e_crclr lt
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
D | r5900.s | 31 # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I. 32 c.lt.s $f0, $f31 33 c.lt.s $f31, $f0
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D | r5900-full.s | 35 # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I. 36 c.lt.s $f0, $f31 37 c.lt.s $f31, $f0
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D | mips64-mips3d.s | 103 cabs.lt.d $fcc0, $f8, $f19 104 cabs.lt.d $fcc2, $f8, $f19 105 cabs.lt.s $fcc0, $f8, $f19 106 cabs.lt.s $fcc2, $f8, $f19 107 cabs.lt.ps $fcc0, $f8, $f19 108 cabs.lt.ps $fcc2, $f8, $f19
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D | mips64-dsp.s | 21 cmp.lt.pw $21,$22 24 cmp.lt.qh $18,$19 27 cmpu.lt.ob $15,$16 30 cmpgu.lt.ob $9,$10,$11
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D | r6-removed.s | 45 c.lt.s $f0,$f2 61 c.lt.ps $f0,$f2 77 c.lt.d $f0,$f2 93 c.lt.s $fcc2, $f0,$f2 109 c.lt.ps $fcc2, $f0,$f2 125 c.lt.d $fcc2, $f0,$f2
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D | mips64-mips3d-incl.d | 103 0+0164 <[^>]*> 4633407c cabs\.lt\.d \$fcc0,\$f8,\$f19 104 0+0168 <[^>]*> 4633427c cabs\.lt\.d \$fcc2,\$f8,\$f19 105 0+016c <[^>]*> 4613407c cabs\.lt\.s \$fcc0,\$f8,\$f19 106 0+0170 <[^>]*> 4613427c cabs\.lt\.s \$fcc2,\$f8,\$f19 107 0+0174 <[^>]*> 46d3407c cabs\.lt\.ps \$fcc0,\$f8,\$f19 108 0+0178 <[^>]*> 46d3427c cabs\.lt\.ps \$fcc2,\$f8,\$f19
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D | mips64-mdmx.s | 73 c.lt.ob $v12, 18 74 c.lt.ob $v12, $v18 75 c.lt.ob $v12, $v18[6] 77 c.lt.qh $v12, 18 78 c.lt.qh $v12, $v18 79 c.lt.qh $v12, $v18[2]
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D | mips64-mips3d.d | 100 0+0164 <[^>]*> 4633407c cabs\.lt\.d \$fcc0,\$f8,\$f19 101 0+0168 <[^>]*> 4633427c cabs\.lt\.d \$fcc2,\$f8,\$f19 102 0+016c <[^>]*> 4613407c cabs\.lt\.s \$fcc0,\$f8,\$f19 103 0+0170 <[^>]*> 4613427c cabs\.lt\.s \$fcc2,\$f8,\$f19 104 0+0174 <[^>]*> 46d3407c cabs\.lt\.ps \$fcc0,\$f8,\$f19 105 0+0178 <[^>]*> 46d3427c cabs\.lt\.ps \$fcc2,\$f8,\$f19
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D | mips32-dsp.s | 91 cmpu.lt.qb $7,$8 94 cmpgu.lt.qb $10,$11,$12 97 cmp.lt.ph $13,$14
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D | mips64-mdmx.d | 54 0+00b0 <[^>]*> 7bd26004 c\.lt\.ob \$v12,0x12 55 0+00b4 <[^>]*> 7ad26004 c\.lt\.ob \$v12,\$v18 56 0+00b8 <[^>]*> 79926004 c\.lt\.ob \$v12,\$v18\[6\] 57 0+00bc <[^>]*> 7bb26004 c\.lt\.qh \$v12,0x12 58 0+00c0 <[^>]*> 7ab26004 c\.lt\.qh \$v12,\$v18 59 0+00c4 <[^>]*> 79326004 c\.lt\.qh \$v12,\$v18\[2\]
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D | r6-removed.l | 44 .*:45: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$f0,\$f2' 60 .*:61: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$f0,\$f2' 76 .*:77: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$f0,\$f2' 92 .*:93: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$fcc2,\$f0,\$f2' 108 .*:109: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$fcc2,\$f0,\$f2' 124 .*:125: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$fcc2,\$f0,\$f2'
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D | vr5400.d | 54 0+00b8 <stuff\+0xb8> c\.lt\.ob \$f0,\$f2 55 0+00bc <stuff\+0xbc> c\.lt\.ob \$f4,\$f6\[2\] 56 0+00c0 <stuff\+0xc0> c\.lt\.ob \$f6,0xf 57 0+00c4 <stuff\+0xc4> c\.lt\.ob \$f4,0x1f
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/toolchain/binutils/binutils-2.27/etc/ |
D | texi2pod.pl | 228 s/</</g; 411 s/\@(?:uref|url|email)\{([^\},]*)\}/<B<$1>>/g; 448 s/</E<lt>/g;
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arc/ |
D | mov.s | 45 mov.lt 0,r1 60 mov.lt.f 0,r2
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D | ror.s | 46 ror.lt r1,r1,1 60 ror.lt.f r2,r2,r2
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