| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| D | mips64-mdmx.s | 9 movf.l $v1, $v12, $fcc5
11 movn.l $v1, $v12, $18
13 movt.l $v1, $v12, $fcc5
15 movz.l $v1, $v12, $18
17 add.ob $v1, $v12, 18
18 add.ob $v1, $v12, $v18
19 add.ob $v1, $v12, $v18[6]
21 add.qh $v1, $v12, 18
22 add.qh $v1, $v12, $v18
23 add.qh $v1, $v12, $v18[2]
[all …]
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| D | mips16-64.d | 16 4: 3b40 ld v0,0\(v1\)
17 6: f000 3b41 ld v0,1\(v1\)
18 a: f000 3b42 ld v0,2\(v1\)
19 e: f000 3b43 ld v0,3\(v1\)
20 12: f000 3b44 ld v0,4\(v1\)
21 16: 3b41 ld v0,8\(v1\)
22 18: 3b42 ld v0,16\(v1\)
23 1a: 3b44 ld v0,32\(v1\)
24 1c: 3b48 ld v0,64\(v1\)
25 1e: 3b50 ld v0,128\(v1\)
[all …]
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| D | mips16.d | 15 4: 3b40 ld v0,0\(v1\)
16 6: f000 3b41 ld v0,1\(v1\)
17 a: f000 3b42 ld v0,2\(v1\)
18 e: f000 3b43 ld v0,3\(v1\)
19 12: f000 3b44 ld v0,4\(v1\)
20 16: 3b41 ld v0,8\(v1\)
21 18: 3b42 ld v0,16\(v1\)
22 1a: 3b44 ld v0,32\(v1\)
23 1c: 3b48 ld v0,64\(v1\)
24 1e: 3b50 ld v0,128\(v1\)
[all …]
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| D | mips64-mdmx.d | 14 0+0010 <[^>]*> 7bd2604b add\.ob \$v1,\$v12,0x12
15 0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
16 0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
17 0+001c <[^>]*> 7bb2604b add\.qh \$v1,\$v12,0x12
18 0+0020 <[^>]*> 7ab2604b add\.qh \$v1,\$v12,\$v18
19 0+0024 <[^>]*> 7932604b add\.qh \$v1,\$v12,\$v18\[2\]
32 0+0058 <[^>]*> 78d26058 alni\.ob \$v1,\$v12,\$v18,6
33 0+005c <[^>]*> 7852605a alni\.qh \$v1,\$v12,\$v18,2
34 0+0060 <[^>]*> 7ab26059 alnv\.ob \$v1,\$v12,\$v18,s5
35 0+0064 <[^>]*> 7ab2605b alnv\.qh \$v1,\$v12,\$v18,s5
[all …]
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| D | sb1-ext-mdmx.s | 14 movf.l $v1, $v12, $fcc5
16 movn.l $v1, $v12, $18
18 movt.l $v1, $v12, $fcc5
20 movz.l $v1, $v12, $18
22 add.ob $v1, $v12, 18
23 add.ob $v1, $v12, $v18
24 add.ob $v1, $v12, $v18[6]
34 alni.ob $v1, $v12, $v18, 6
36 alnv.ob $v1, $v12, $v18, $21
38 and.ob $v1, $v12, 18
[all …]
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| D | sb1-ext-mdmx.d | 14 0+0010 <[^>]*> 7bd2604b add\.ob \$v1,\$v12,0x12
15 0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
16 0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
23 0+0034 <[^>]*> 78d26058 alni\.ob \$v1,\$v12,\$v18,6
24 0+0038 <[^>]*> 7ab26059 alnv\.ob \$v1,\$v12,\$v18,s5
25 0+003c <[^>]*> 7bd2604c and\.ob \$v1,\$v12,0x12
26 0+0040 <[^>]*> 7ad2604c and\.ob \$v1,\$v12,\$v18
27 0+0044 <[^>]*> 7992604c and\.ob \$v1,\$v12,\$v18\[6\]
37 0+006c <[^>]*> 7bd26047 max\.ob \$v1,\$v12,0x12
38 0+0070 <[^>]*> 7ad26047 max\.ob \$v1,\$v12,\$v18
[all …]
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| D | r6-64-n32.d | 11 0+0000 <[^>]*> 0064109c dmul v0,v1,a0
12 0+0004 <[^>]*> 006410dc dmuh v0,v1,a0
13 0+0008 <[^>]*> 0064109e ddiv v0,v1,a0
14 0+000c <[^>]*> 0064109d dmulu v0,v1,a0
15 0+0010 <[^>]*> 006410dd dmuhu v0,v1,a0
16 0+0014 <[^>]*> 006410de dmod v0,v1,a0
17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
18 0+001c <[^>]*> 006410df dmodu v0,v1,a0
19 0+0020 <[^>]*> 00641015 dlsa v0,v1,a0,0x1
20 0+0024 <[^>]*> 006410d5 dlsa v0,v1,a0,0x4
[all …]
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| D | r6-64-n64.d | 11 0+0000 <[^>]*> 0064109c dmul v0,v1,a0
12 0+0004 <[^>]*> 006410dc dmuh v0,v1,a0
13 0+0008 <[^>]*> 0064109e ddiv v0,v1,a0
14 0+000c <[^>]*> 0064109d dmulu v0,v1,a0
15 0+0010 <[^>]*> 006410dd dmuhu v0,v1,a0
16 0+0014 <[^>]*> 006410de dmod v0,v1,a0
17 0+0018 <[^>]*> 0064109f ddivu v0,v1,a0
18 0+001c <[^>]*> 006410df dmodu v0,v1,a0
19 0+0020 <[^>]*> 00641015 dlsa v0,v1,a0,0x1
20 0+0024 <[^>]*> 006410d5 dlsa v0,v1,a0,0x4
[all …]
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| D | micromips-branch-relax.d | 14 [ 0-9a-f]+: 05d8 addu v1,a0,a1
15 [ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
17 [ 0-9a-f]+: 05d8 addu v1,a0,a1
18 [ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
20 [ 0-9a-f]+: 05d8 addu v1,a0,a1
23 [ 0-9a-f]+: 05d8 addu v1,a0,a1
26 [ 0-9a-f]+: 05d8 addu v1,a0,a1
29 [ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
32 [ 0-9a-f]+: 05d8 addu v1,a0,a1
33 [ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[all …]
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| D | micromips.d | 57 [ 0-9a-f]+: edff li v1,-1
81 [ 0-9a-f]+: 0c76 move v1,s6
93 [ 0-9a-f]+: 0c03 move zero,v1
136 [ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
138 [ 0-9a-f]+: 0c43 move v0,v1
139 [ 0-9a-f]+: 0060 1190 neg v0,v1
160 [ 0-9a-f]+: 0083 1110 add v0,v1,a0
170 [ 0-9a-f]+: 1064 8000 addi v1,a0,-32768
171 [ 0-9a-f]+: 1064 0000 addi v1,a0,0
172 [ 0-9a-f]+: 1064 7fff addi v1,a0,32767
[all …]
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| D | micromips-trap.d | 57 [ 0-9a-f]+: edff li v1,-1
81 [ 0-9a-f]+: 0c76 move v1,s6
93 [ 0-9a-f]+: 0c03 move zero,v1
136 [ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
138 [ 0-9a-f]+: 0c43 move v0,v1
139 [ 0-9a-f]+: 0060 1190 neg v0,v1
160 [ 0-9a-f]+: 0083 1110 add v0,v1,a0
170 [ 0-9a-f]+: 1064 8000 addi v1,a0,-32768
171 [ 0-9a-f]+: 1064 0000 addi v1,a0,0
172 [ 0-9a-f]+: 1064 7fff addi v1,a0,32767
[all …]
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| D | micromips-insn32.d | 56 [ 0-9a-f]+: 3060 ffff li v1,-1
80 [ 0-9a-f]+: 0016 1a90 move v1,s6
92 [ 0-9a-f]+: 0003 0290 move zero,v1
124 [ 0-9a-f]+: 4043 fffe bgez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
126 [ 0-9a-f]+: 0003 1290 move v0,v1
127 [ 0-9a-f]+: 0060 1190 neg v0,v1
148 [ 0-9a-f]+: 0083 1110 add v0,v1,a0
158 [ 0-9a-f]+: 1064 8000 addi v1,a0,-32768
159 [ 0-9a-f]+: 1064 0000 addi v1,a0,0
160 [ 0-9a-f]+: 1064 7fff addi v1,a0,32767
[all …]
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| D | trap20.d | 8 0+0000 <[^>]*> teq zero,v1
9 0+0004 <[^>]*> teq zero,v1,0x1
10 0+0008 <[^>]*> tge zero,v1
11 0+000c <[^>]*> tge zero,v1,0x3
12 0+0010 <[^>]*> tgeu zero,v1
13 0+0014 <[^>]*> tgeu zero,v1,0x7
14 0+0018 <[^>]*> tlt zero,v1
15 0+001c <[^>]*> tlt zero,v1,0x1f
16 0+0020 <[^>]*> tltu zero,v1
17 0+0024 <[^>]*> tltu zero,v1,0xff
[all …]
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| D | micromips-branch-relax-pic.d | 14 [ 0-9a-f]+: 05d8 addu v1,a0,a1
15 [ 0-9a-f]+: 9403 fffe beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
17 [ 0-9a-f]+: 05d8 addu v1,a0,a1
18 [ 0-9a-f]+: b403 fffe bnez v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
20 [ 0-9a-f]+: 05d8 addu v1,a0,a1
23 [ 0-9a-f]+: 05d8 addu v1,a0,a1
26 [ 0-9a-f]+: 05d8 addu v1,a0,a1
29 [ 0-9a-f]+: 00a4 1950 addu v1,a0,a1
32 [ 0-9a-f]+: 05d8 addu v1,a0,a1
33 [ 0-9a-f]+: 8dff beqz v1,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[all …]
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| D | ldstla-eabi64.d | 18 .* daddu a0,a0,v1
21 .* daddu a0,a0,v1
26 .* daddu a0,a0,v1
31 .* daddu a0,a0,v1
44 .* daddu a0,a0,v1
52 .* daddu a0,a0,v1
57 .* daddu a0,a0,v1
69 .* daddu a0,a0,v1
78 .* daddu a0,a0,v1
86 .* daddu a0,a0,v1
[all …]
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| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/aarch64/ |
| D | advsimd-fp16.d | 9 [0-9a-f]+: 4e63c441 fmaxnm v1.2d, v2.2d, v3.2d
10 [0-9a-f]+: 0e23c441 fmaxnm v1.2s, v2.2s, v3.2s
11 [0-9a-f]+: 4e23c441 fmaxnm v1.4s, v2.4s, v3.4s
13 [0-9a-f]+: 0e430441 fmaxnm v1.4h, v2.4h, v3.4h
15 [0-9a-f]+: 4e430441 fmaxnm v1.8h, v2.8h, v3.8h
16 [0-9a-f]+: 6e63c441 fmaxnmp v1.2d, v2.2d, v3.2d
17 [0-9a-f]+: 2e23c441 fmaxnmp v1.2s, v2.2s, v3.2s
18 [0-9a-f]+: 6e23c441 fmaxnmp v1.4s, v2.4s, v3.4s
20 [0-9a-f]+: 2e430441 fmaxnmp v1.4h, v2.4h, v3.4h
22 [0-9a-f]+: 6e430441 fmaxnmp v1.8h, v2.8h, v3.8h
[all …]
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| D | rdma-directive.d | 11 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
12 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
13 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
14 c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
15 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
16 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
17 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
18 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
23 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
24 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
[all …]
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| D | rdma.d | 10 0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
11 4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
12 8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
13 c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
14 10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
15 14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
16 18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
17 1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
22 30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
23 34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
[all …]
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| D | advsimd-fp16.s | 7 \op v1.2d, v2.2d, v3.2d
8 \op v1.2s, v2.2s, v3.2s
9 \op v1.4s, v2.4s, v3.4s
11 \op v1.4h, v2.4h, v3.4h
13 \op v1.8h, v2.8h, v3.8h
64 \op v0.2d, v1.2d, #0.0
65 \op v0.2s, v1.2s, #0.0
66 \op v0.4s, v1.4s, #0.0
67 \op v0.4h, v1.4h, #0.0
68 \op v0.8h, v1.8h, #0.0
[all …]
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| D | neon-vfp-reglist-post.s | 11 \inst\()1 {v0.\type, v1.\type}, [x0], #16
12 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
13 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #32
24 \inst\()1 {v0.\type, v1.\type}, [x0], #32
25 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #48
26 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], #64
37 \inst\()1 {v0.\type, v1.\type}, [x0], \postreg
38 \inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], \postreg
39 \inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}, [x0], \postreg
49 \inst\()2 {v0.\type, v1.\type}, [x0], #16
[all …]
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| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-mips-elf/ |
| D | tlsdyn-o32-1.d | 32 .*: 3c030000 lui v1,0x0
33 .*: 24638000 addiu v1,v1,-32768
34 .*: 00621821 addu v1,v1,v0
36 .*: 8f838024 lw v1,-32732\(gp\)
38 .*: 00621821 addu v1,v1,v0
39 .*: 8f838030 lw v1,-32720\(gp\)
41 .*: 00621821 addu v1,v1,v0
43 .*: 3c030000 lui v1,0x0
44 .*: 24639004 addiu v1,v1,-28668
45 .*: 00621821 addu v1,v1,v0
[all …]
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| D | tlsdyn-o32-3.d | 32 .*: 3c030000 lui v1,0x0
33 .*: 24638000 addiu v1,v1,-32768
34 .*: 00621821 addu v1,v1,v0
36 .*: 8f838024 lw v1,-32732\(gp\)
38 .*: 00621821 addu v1,v1,v0
39 .*: 8f838030 lw v1,-32720\(gp\)
41 .*: 00621821 addu v1,v1,v0
43 .*: 3c030000 lui v1,0x0
44 .*: 24639004 addiu v1,v1,-28668
45 .*: 00621821 addu v1,v1,v0
[all …]
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| D | tlsdyn-o32-2.d | 32 .*: 3c030000 lui v1,0x0
33 .*: 24638000 addiu v1,v1,-32768
34 .*: 00621821 addu v1,v1,v0
36 .*: 8f838024 lw v1,-32732\(gp\)
38 .*: 00621821 addu v1,v1,v0
39 .*: 8f838030 lw v1,-32720\(gp\)
41 .*: 00621821 addu v1,v1,v0
43 .*: 3c030000 lui v1,0x0
44 .*: 24639004 addiu v1,v1,-28668
45 .*: 00621821 addu v1,v1,v0
[all …]
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| D | tlsdyn-o32.d | 32 .*: 3c030000 lui v1,0x0
33 .*: 24638000 addiu v1,v1,-32768
34 .*: 00621821 addu v1,v1,v0
36 .*: 8f83801c lw v1,-32740\(gp\)
38 .*: 00621821 addu v1,v1,v0
39 .*: 8f838030 lw v1,-32720\(gp\)
41 .*: 00621821 addu v1,v1,v0
43 .*: 3c030000 lui v1,0x0
44 .*: 24639004 addiu v1,v1,-28668
45 .*: 00621821 addu v1,v1,v0
|
| /toolchain/binutils/binutils-2.27/binutils/testsuite/binutils-all/mips/ |
| D | mips16-undecoded.d | 97 [0-9a-f]+ <[^>]*> f500 3260 sll v0,v1,20
98 [0-9a-f]+ <[^>]*> f500 3260 sll v0,v1,20
99 [0-9a-f]+ <[^>]*> f500 3264 sll v0,v1,20
100 [0-9a-f]+ <[^>]*> f500 3268 sll v0,v1,20
101 [0-9a-f]+ <[^>]*> f500 3270 sll v0,v1,20
102 [0-9a-f]+ <[^>]*> f501 3260 sll v0,v1,20
103 [0-9a-f]+ <[^>]*> f502 3260 sll v0,v1,20
104 [0-9a-f]+ <[^>]*> f504 3260 sll v0,v1,20
105 [0-9a-f]+ <[^>]*> f508 3260 sll v0,v1,20
106 [0-9a-f]+ <[^>]*> f510 3260 sll v0,v1,20
[all …]
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