1 /* alpha-opc.c -- Alpha AXP opcode list
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@cygnus.com>,
4 patterned after the PPC opcode handling written by Ian Lance Taylor.
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include "sysdep.h"
24 #include <stdio.h>
25 #include "opcode/alpha.h"
26 #include "bfd.h"
27 #include "opintl.h"
28
29 /* This file holds the Alpha AXP opcode table. The opcode table includes
30 almost all of the extended instruction mnemonics. This permits the
31 disassembler to use them, and simplifies the assembler logic, at the
32 cost of increasing the table size. The table is strictly constant
33 data, so the compiler should be able to put it in the text segment.
34
35 This file also holds the operand table. All knowledge about inserting
36 and extracting operands from instructions is kept in this file.
37
38 The information for the base instruction set was compiled from the
39 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
40 version 2.
41
42 The information for the post-ev5 architecture extensions BWX, CIX and
43 MAX came from version 3 of this same document, which is also available
44 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
45 /literature/alphahb2.pdf
46
47 The information for the EV4 PALcode instructions was compiled from
48 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
49 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
50 revision dated June 1994.
51
52 The information for the EV5 PALcode instructions was compiled from
53 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
54 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
55
56 /* The RB field when it is the same as the RA field in the same insn.
57 This operand is marked fake. The insertion function just copies
58 the RA field into the RB field, and the extraction function just
59 checks that the fields are the same. */
60
61 static unsigned
insert_rba(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)62 insert_rba (unsigned insn,
63 int value ATTRIBUTE_UNUSED,
64 const char **errmsg ATTRIBUTE_UNUSED)
65 {
66 return insn | (((insn >> 21) & 0x1f) << 16);
67 }
68
69 static int
extract_rba(unsigned insn,int * invalid)70 extract_rba (unsigned insn, int *invalid)
71 {
72 if (invalid != (int *) NULL
73 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
74 *invalid = 1;
75 return 0;
76 }
77
78 /* The same for the RC field. */
79
80 static unsigned
insert_rca(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)81 insert_rca (unsigned insn,
82 int value ATTRIBUTE_UNUSED,
83 const char **errmsg ATTRIBUTE_UNUSED)
84 {
85 return insn | ((insn >> 21) & 0x1f);
86 }
87
88 static int
extract_rca(unsigned insn,int * invalid)89 extract_rca (unsigned insn, int *invalid)
90 {
91 if (invalid != (int *) NULL
92 && ((insn >> 21) & 0x1f) != (insn & 0x1f))
93 *invalid = 1;
94 return 0;
95 }
96
97 /* Fake arguments in which the registers must be set to ZERO. */
98
99 static unsigned
insert_za(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)100 insert_za (unsigned insn,
101 int value ATTRIBUTE_UNUSED,
102 const char **errmsg ATTRIBUTE_UNUSED)
103 {
104 return insn | (31 << 21);
105 }
106
107 static int
extract_za(unsigned insn,int * invalid)108 extract_za (unsigned insn, int *invalid)
109 {
110 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
111 *invalid = 1;
112 return 0;
113 }
114
115 static unsigned
insert_zb(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)116 insert_zb (unsigned insn,
117 int value ATTRIBUTE_UNUSED,
118 const char **errmsg ATTRIBUTE_UNUSED)
119 {
120 return insn | (31 << 16);
121 }
122
123 static int
extract_zb(unsigned insn,int * invalid)124 extract_zb (unsigned insn, int *invalid)
125 {
126 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
127 *invalid = 1;
128 return 0;
129 }
130
131 static unsigned
insert_zc(unsigned insn,int value ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)132 insert_zc (unsigned insn,
133 int value ATTRIBUTE_UNUSED,
134 const char **errmsg ATTRIBUTE_UNUSED)
135 {
136 return insn | 31;
137 }
138
139 static int
extract_zc(unsigned insn,int * invalid)140 extract_zc (unsigned insn, int *invalid)
141 {
142 if (invalid != (int *) NULL && (insn & 0x1f) != 31)
143 *invalid = 1;
144 return 0;
145 }
146
147
148 /* The displacement field of a Branch format insn. */
149
150 static unsigned
insert_bdisp(unsigned insn,int value,const char ** errmsg)151 insert_bdisp (unsigned insn, int value, const char **errmsg)
152 {
153 if (errmsg != (const char **)NULL && (value & 3))
154 *errmsg = _("branch operand unaligned");
155 return insn | ((value / 4) & 0x1FFFFF);
156 }
157
158 static int
extract_bdisp(unsigned insn,int * invalid ATTRIBUTE_UNUSED)159 extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
160 {
161 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
162 }
163
164 /* The hint field of a JMP/JSR insn. */
165
166 static unsigned
insert_jhint(unsigned insn,int value,const char ** errmsg)167 insert_jhint (unsigned insn, int value, const char **errmsg)
168 {
169 if (errmsg != (const char **)NULL && (value & 3))
170 *errmsg = _("jump hint unaligned");
171 return insn | ((value / 4) & 0x3FFF);
172 }
173
174 static int
extract_jhint(unsigned insn,int * invalid ATTRIBUTE_UNUSED)175 extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
176 {
177 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
178 }
179
180 /* The hint field of an EV6 HW_JMP/JSR insn. */
181
182 static unsigned
insert_ev6hwjhint(unsigned insn,int value,const char ** errmsg)183 insert_ev6hwjhint (unsigned insn, int value, const char **errmsg)
184 {
185 if (errmsg != (const char **)NULL && (value & 3))
186 *errmsg = _("jump hint unaligned");
187 return insn | ((value / 4) & 0x1FFF);
188 }
189
190 static int
extract_ev6hwjhint(unsigned insn,int * invalid ATTRIBUTE_UNUSED)191 extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
192 {
193 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
194 }
195
196 /* The operands table. */
197
198 const struct alpha_operand alpha_operands[] =
199 {
200 /* The fields are bits, shift, insert, extract, flags */
201 /* The zero index is used to indicate end-of-list */
202 #define UNUSED 0
203 { 0, 0, 0, 0, 0, 0 },
204
205 /* The plain integer register fields. */
206 #define RA (UNUSED + 1)
207 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
208 #define RB (RA + 1)
209 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
210 #define RC (RB + 1)
211 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
212
213 /* The plain fp register fields. */
214 #define FA (RC + 1)
215 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
216 #define FB (FA + 1)
217 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
218 #define FC (FB + 1)
219 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
220
221 /* The integer registers when they are ZERO. */
222 #define ZA (FC + 1)
223 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
224 #define ZB (ZA + 1)
225 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
226 #define ZC (ZB + 1)
227 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
228
229 /* The RB field when it needs parentheses. */
230 #define PRB (ZC + 1)
231 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
232
233 /* The RB field when it needs parentheses _and_ a preceding comma. */
234 #define CPRB (PRB + 1)
235 { 5, 16, 0,
236 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
237
238 /* The RB field when it must be the same as the RA field. */
239 #define RBA (CPRB + 1)
240 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
241
242 /* The RC field when it must be the same as the RB field. */
243 #define RCA (RBA + 1)
244 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
245
246 /* The RC field when it can *default* to RA. */
247 #define DRC1 (RCA + 1)
248 { 5, 0, 0,
249 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
250
251 /* The RC field when it can *default* to RB. */
252 #define DRC2 (DRC1 + 1)
253 { 5, 0, 0,
254 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
255
256 /* The FC field when it can *default* to RA. */
257 #define DFC1 (DRC2 + 1)
258 { 5, 0, 0,
259 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
260
261 /* The FC field when it can *default* to RB. */
262 #define DFC2 (DFC1 + 1)
263 { 5, 0, 0,
264 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
265
266 /* The unsigned 8-bit literal of Operate format insns. */
267 #define LIT (DFC2 + 1)
268 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
269
270 /* The signed 16-bit displacement of Memory format insns. From here
271 we can't tell what relocation should be used, so don't use a default. */
272 #define MDISP (LIT + 1)
273 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
274
275 /* The signed "23-bit" aligned displacement of Branch format insns. */
276 #define BDISP (MDISP + 1)
277 { 21, 0, BFD_RELOC_23_PCREL_S2,
278 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
279
280 /* The 26-bit PALcode function */
281 #define PALFN (BDISP + 1)
282 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
283
284 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */
285 #define JMPHINT (PALFN + 1)
286 { 14, 0, BFD_RELOC_ALPHA_HINT,
287 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
288 insert_jhint, extract_jhint },
289
290 /* The optional hint to RET/JSR_COROUTINE. */
291 #define RETHINT (JMPHINT + 1)
292 { 14, 0, -RETHINT,
293 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
294
295 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */
296 #define EV4HWDISP (RETHINT + 1)
297 #define EV6HWDISP (EV4HWDISP)
298 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
299
300 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */
301 #define EV4HWINDEX (EV4HWDISP + 1)
302 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
303
304 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
305 that occur in DEC PALcode. */
306 #define EV4EXTHWINDEX (EV4HWINDEX + 1)
307 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
308
309 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */
310 #define EV5HWDISP (EV4EXTHWINDEX + 1)
311 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
312
313 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */
314 #define EV5HWINDEX (EV5HWDISP + 1)
315 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
316
317 /* The 16-bit combined index/scoreboard mask for the ev6
318 hw_m[ft]pr (pal19/pal1d) insns. */
319 #define EV6HWINDEX (EV5HWINDEX + 1)
320 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
321
322 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */
323 #define EV6HWJMPHINT (EV6HWINDEX+ 1)
324 { 8, 0, -EV6HWJMPHINT,
325 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
326 insert_ev6hwjhint, extract_ev6hwjhint }
327 };
328
329 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
330
331
332 /* Macros used to form opcodes. */
333
334 /* The main opcode. */
335 #define OP(x) (((x) & 0x3F) << 26)
336 #define OP_MASK 0xFC000000
337
338 /* Branch format instructions. */
339 #define BRA_(oo) OP(oo)
340 #define BRA_MASK OP_MASK
341 #define BRA(oo) BRA_(oo), BRA_MASK
342
343 /* Floating point format instructions. */
344 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
345 #define FP_MASK (OP_MASK | 0xFFE0)
346 #define FP(oo,fff) FP_(oo,fff), FP_MASK
347
348 /* Memory format instructions. */
349 #define MEM_(oo) OP(oo)
350 #define MEM_MASK OP_MASK
351 #define MEM(oo) MEM_(oo), MEM_MASK
352
353 /* Memory/Func Code format instructions. */
354 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
355 #define MFC_MASK (OP_MASK | 0xFFFF)
356 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
357
358 /* Memory/Branch format instructions. */
359 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
360 #define MBR_MASK (OP_MASK | 0xC000)
361 #define MBR(oo,h) MBR_(oo,h), MBR_MASK
362
363 /* Operate format instructions. The OPRL variant specifies a
364 literal second argument. */
365 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
366 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
367 #define OPR_MASK (OP_MASK | 0x1FE0)
368 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
369 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
370
371 /* Generic PALcode format instructions. */
372 #define PCD_(oo) OP(oo)
373 #define PCD_MASK OP_MASK
374 #define PCD(oo) PCD_(oo), PCD_MASK
375
376 /* Specific PALcode instructions. */
377 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
378 #define SPCD_MASK 0xFFFFFFFF
379 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
380
381 /* Hardware memory (hw_{ld,st}) instructions. */
382 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
383 #define EV4HWMEM_MASK (OP_MASK | 0xF000)
384 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
385
386 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
387 #define EV5HWMEM_MASK (OP_MASK | 0xF800)
388 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
389
390 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
391 #define EV6HWMEM_MASK (OP_MASK | 0xF000)
392 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
393
394 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
395 #define EV6HWMBR_MASK (OP_MASK | 0xE000)
396 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
397
398 /* Abbreviations for instruction subsets. */
399 #define BASE AXP_OPCODE_BASE
400 #define EV4 AXP_OPCODE_EV4
401 #define EV5 AXP_OPCODE_EV5
402 #define EV6 AXP_OPCODE_EV6
403 #define BWX AXP_OPCODE_BWX
404 #define CIX AXP_OPCODE_CIX
405 #define MAX AXP_OPCODE_MAX
406
407 /* Common combinations of arguments. */
408 #define ARG_NONE { 0 }
409 #define ARG_BRA { RA, BDISP }
410 #define ARG_FBRA { FA, BDISP }
411 #define ARG_FP { FA, FB, DFC1 }
412 #define ARG_FPZ1 { ZA, FB, DFC1 }
413 #define ARG_MEM { RA, MDISP, PRB }
414 #define ARG_FMEM { FA, MDISP, PRB }
415 #define ARG_OPR { RA, RB, DRC1 }
416 #define ARG_OPRL { RA, LIT, DRC1 }
417 #define ARG_OPRZ1 { ZA, RB, DRC1 }
418 #define ARG_OPRLZ1 { ZA, LIT, RC }
419 #define ARG_PCD { PALFN }
420 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
421 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
422 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
423 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
424
425 /* The opcode table.
426
427 The format of the opcode table is:
428
429 NAME OPCODE MASK { OPERANDS }
430
431 NAME is the name of the instruction.
432
433 OPCODE is the instruction opcode.
434
435 MASK is the opcode mask; this is used to tell the disassembler
436 which bits in the actual opcode must match OPCODE.
437
438 OPERANDS is the list of operands.
439
440 The preceding macros merge the text of the OPCODE and MASK fields.
441
442 The disassembler reads the table in order and prints the first
443 instruction which matches, so this table is sorted to put more
444 specific instructions before more general instructions.
445
446 Otherwise, it is sorted by major opcode and minor function code.
447
448 There are three classes of not-really-instructions in this table:
449
450 ALIAS is another name for another instruction. Some of
451 these come from the Architecture Handbook, some
452 come from the original gas opcode tables. In all
453 cases, the functionality of the opcode is unchanged.
454
455 PSEUDO a stylized code form endorsed by Chapter A.4 of the
456 Architecture Handbook.
457
458 EXTRA a stylized code form found in the original gas tables.
459
460 And two annotations:
461
462 EV56 BUT opcodes that are officially introduced as of the ev56,
463 but with defined results on previous implementations.
464
465 EV56 UNA opcodes that were introduced as of the ev56 with
466 presumably undefined results on previous implementations
467 that were not assigned to a particular extension. */
468
469 const struct alpha_opcode alpha_opcodes[] =
470 {
471 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
472 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
473 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
474 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
475 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
476 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
477 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
478 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
479 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
480 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
481 { "call_pal", PCD(0x00), BASE, ARG_PCD },
482 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
483
484 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */
485 { "lda", MEM(0x08), BASE, ARG_MEM },
486 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */
487 { "ldah", MEM(0x09), BASE, ARG_MEM },
488 { "ldbu", MEM(0x0A), BWX, ARG_MEM },
489 { "unop", MEM_(0x0B) | (30 << 16),
490 MEM_MASK, BASE, { ZA } }, /* pseudo */
491 { "ldq_u", MEM(0x0B), BASE, ARG_MEM },
492 { "ldwu", MEM(0x0C), BWX, ARG_MEM },
493 { "stw", MEM(0x0D), BWX, ARG_MEM },
494 { "stb", MEM(0x0E), BWX, ARG_MEM },
495 { "stq_u", MEM(0x0F), BASE, ARG_MEM },
496
497 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
498 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */
499 { "addl", OPR(0x10,0x00), BASE, ARG_OPR },
500 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL },
501 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR },
502 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL },
503 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
504 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */
505 { "subl", OPR(0x10,0x09), BASE, ARG_OPR },
506 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL },
507 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR },
508 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL },
509 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR },
510 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL },
511 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR },
512 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL },
513 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR },
514 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL },
515 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR },
516 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL },
517 { "addq", OPR(0x10,0x20), BASE, ARG_OPR },
518 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL },
519 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR },
520 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL },
521 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
522 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */
523 { "subq", OPR(0x10,0x29), BASE, ARG_OPR },
524 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL },
525 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR },
526 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL },
527 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR },
528 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL },
529 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR },
530 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL },
531 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR },
532 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL },
533 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR },
534 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL },
535 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR },
536 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL },
537 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
538 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */
539 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR },
540 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL },
541 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR },
542 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL },
543 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR },
544 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL },
545 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
546 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */
547 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR },
548 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL },
549 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR },
550 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL },
551
552 { "and", OPR(0x11,0x00), BASE, ARG_OPR },
553 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL },
554 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */
555 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
556 { "bic", OPR(0x11,0x08), BASE, ARG_OPR },
557 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL },
558 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR },
559 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL },
560 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR },
561 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL },
562 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
563 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
564 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
565 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
566 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
567 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */
568 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
569 { "bis", OPR(0x11,0x20), BASE, ARG_OPR },
570 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL },
571 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR },
572 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL },
573 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR },
574 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL },
575 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
576 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */
577 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR },
578 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL },
579 { "xor", OPR(0x11,0x40), BASE, ARG_OPR },
580 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL },
581 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR },
582 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL },
583 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR },
584 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL },
585 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR },
586 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL },
587 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */
588 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
589 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
590 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */
591 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR },
592 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL },
593 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
594 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
595 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
596 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
597
598 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
599 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },
600 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR },
601 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL },
602 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR },
603 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL },
604 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR },
605 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL },
606 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR },
607 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL },
608 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR },
609 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL },
610 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR },
611 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL },
612 { "extll", OPR(0x12,0x26), BASE, ARG_OPR },
613 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL },
614 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR },
615 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL },
616 { "zap", OPR(0x12,0x30), BASE, ARG_OPR },
617 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL },
618 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR },
619 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL },
620 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR },
621 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL },
622 { "srl", OPR(0x12,0x34), BASE, ARG_OPR },
623 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL },
624 { "extql", OPR(0x12,0x36), BASE, ARG_OPR },
625 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL },
626 { "sll", OPR(0x12,0x39), BASE, ARG_OPR },
627 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL },
628 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR },
629 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL },
630 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR },
631 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL },
632 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR },
633 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL },
634 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR },
635 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL },
636 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR },
637 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL },
638 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR },
639 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL },
640 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR },
641 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL },
642 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR },
643 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL },
644 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR },
645 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL },
646 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR },
647 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL },
648 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR },
649 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL },
650
651 { "mull", OPR(0x13,0x00), BASE, ARG_OPR },
652 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL },
653 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR },
654 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL },
655 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },
656 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL },
657 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR },
658 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL },
659 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR },
660 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL },
661
662 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
663 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
664 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
665 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
666 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
667 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
668 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
669 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
670 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
671 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 },
672 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 },
673 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 },
674 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 },
675 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 },
676 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 },
677 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 },
678 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 },
679 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 },
680 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 },
681 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 },
682 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 },
683 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 },
684 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 },
685 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 },
686 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 },
687 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 },
688 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 },
689 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 },
690 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 },
691 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 },
692 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 },
693 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 },
694 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 },
695 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 },
696 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 },
697 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 },
698 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 },
699 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 },
700 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 },
701 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 },
702 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 },
703 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 },
704 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 },
705 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 },
706 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 },
707 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 },
708 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 },
709 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 },
710 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 },
711 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 },
712 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 },
713
714 { "addf/c", FP(0x15,0x000), BASE, ARG_FP },
715 { "subf/c", FP(0x15,0x001), BASE, ARG_FP },
716 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP },
717 { "divf/c", FP(0x15,0x003), BASE, ARG_FP },
718 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 },
719 { "addg/c", FP(0x15,0x020), BASE, ARG_FP },
720 { "subg/c", FP(0x15,0x021), BASE, ARG_FP },
721 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP },
722 { "divg/c", FP(0x15,0x023), BASE, ARG_FP },
723 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 },
724 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 },
725 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 },
726 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 },
727 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 },
728 { "addf", FP(0x15,0x080), BASE, ARG_FP },
729 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */
730 { "subf", FP(0x15,0x081), BASE, ARG_FP },
731 { "mulf", FP(0x15,0x082), BASE, ARG_FP },
732 { "divf", FP(0x15,0x083), BASE, ARG_FP },
733 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 },
734 { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
735 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
736 { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
737 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
738 { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
739 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP },
740 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP },
741 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP },
742 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 },
743 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 },
744 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 },
745 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 },
746 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 },
747 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP },
748 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP },
749 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP },
750 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP },
751 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 },
752 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP },
753 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP },
754 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
755 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP },
756 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 },
757 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 },
758 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 },
759 { "addf/u", FP(0x15,0x180), BASE, ARG_FP },
760 { "subf/u", FP(0x15,0x181), BASE, ARG_FP },
761 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP },
762 { "divf/u", FP(0x15,0x183), BASE, ARG_FP },
763 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 },
764 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP },
765 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP },
766 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP },
767 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP },
768 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 },
769 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 },
770 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 },
771 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP },
772 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP },
773 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP },
774 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP },
775 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 },
776 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP },
777 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP },
778 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP },
779 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP },
780 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 },
781 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 },
782 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 },
783 { "addf/s", FP(0x15,0x480), BASE, ARG_FP },
784 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */
785 { "subf/s", FP(0x15,0x481), BASE, ARG_FP },
786 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP },
787 { "divf/s", FP(0x15,0x483), BASE, ARG_FP },
788 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 },
789 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP },
790 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */
791 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP },
792 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP },
793 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP },
794 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP },
795 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP },
796 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP },
797 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 },
798 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 },
799 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 },
800 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP },
801 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP },
802 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP },
803 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP },
804 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 },
805 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP },
806 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP },
807 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP },
808 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP },
809 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 },
810 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 },
811 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 },
812 { "addf/su", FP(0x15,0x580), BASE, ARG_FP },
813 { "subf/su", FP(0x15,0x581), BASE, ARG_FP },
814 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP },
815 { "divf/su", FP(0x15,0x583), BASE, ARG_FP },
816 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 },
817 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP },
818 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP },
819 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP },
820 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP },
821 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 },
822 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 },
823 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 },
824
825 { "adds/c", FP(0x16,0x000), BASE, ARG_FP },
826 { "subs/c", FP(0x16,0x001), BASE, ARG_FP },
827 { "muls/c", FP(0x16,0x002), BASE, ARG_FP },
828 { "divs/c", FP(0x16,0x003), BASE, ARG_FP },
829 { "addt/c", FP(0x16,0x020), BASE, ARG_FP },
830 { "subt/c", FP(0x16,0x021), BASE, ARG_FP },
831 { "mult/c", FP(0x16,0x022), BASE, ARG_FP },
832 { "divt/c", FP(0x16,0x023), BASE, ARG_FP },
833 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 },
834 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 },
835 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 },
836 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 },
837 { "adds/m", FP(0x16,0x040), BASE, ARG_FP },
838 { "subs/m", FP(0x16,0x041), BASE, ARG_FP },
839 { "muls/m", FP(0x16,0x042), BASE, ARG_FP },
840 { "divs/m", FP(0x16,0x043), BASE, ARG_FP },
841 { "addt/m", FP(0x16,0x060), BASE, ARG_FP },
842 { "subt/m", FP(0x16,0x061), BASE, ARG_FP },
843 { "mult/m", FP(0x16,0x062), BASE, ARG_FP },
844 { "divt/m", FP(0x16,0x063), BASE, ARG_FP },
845 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 },
846 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 },
847 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 },
848 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 },
849 { "adds", FP(0x16,0x080), BASE, ARG_FP },
850 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */
851 { "subs", FP(0x16,0x081), BASE, ARG_FP },
852 { "muls", FP(0x16,0x082), BASE, ARG_FP },
853 { "divs", FP(0x16,0x083), BASE, ARG_FP },
854 { "addt", FP(0x16,0x0A0), BASE, ARG_FP },
855 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
856 { "subt", FP(0x16,0x0A1), BASE, ARG_FP },
857 { "mult", FP(0x16,0x0A2), BASE, ARG_FP },
858 { "divt", FP(0x16,0x0A3), BASE, ARG_FP },
859 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP },
860 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP },
861 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP },
862 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP },
863 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 },
864 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 },
865 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 },
866 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 },
867 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP },
868 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP },
869 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP },
870 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP },
871 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP },
872 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP },
873 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP },
874 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP },
875 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 },
876 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 },
877 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 },
878 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 },
879 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP },
880 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP },
881 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP },
882 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP },
883 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP },
884 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP },
885 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
886 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP },
887 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 },
888 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 },
889 { "adds/um", FP(0x16,0x140), BASE, ARG_FP },
890 { "subs/um", FP(0x16,0x141), BASE, ARG_FP },
891 { "muls/um", FP(0x16,0x142), BASE, ARG_FP },
892 { "divs/um", FP(0x16,0x143), BASE, ARG_FP },
893 { "addt/um", FP(0x16,0x160), BASE, ARG_FP },
894 { "subt/um", FP(0x16,0x161), BASE, ARG_FP },
895 { "mult/um", FP(0x16,0x162), BASE, ARG_FP },
896 { "divt/um", FP(0x16,0x163), BASE, ARG_FP },
897 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 },
898 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 },
899 { "adds/u", FP(0x16,0x180), BASE, ARG_FP },
900 { "subs/u", FP(0x16,0x181), BASE, ARG_FP },
901 { "muls/u", FP(0x16,0x182), BASE, ARG_FP },
902 { "divs/u", FP(0x16,0x183), BASE, ARG_FP },
903 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP },
904 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP },
905 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP },
906 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP },
907 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 },
908 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 },
909 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP },
910 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP },
911 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP },
912 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP },
913 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP },
914 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP },
915 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP },
916 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP },
917 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 },
918 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 },
919 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 },
920 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP },
921 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP },
922 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP },
923 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP },
924 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP },
925 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP },
926 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP },
927 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP },
928 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 },
929 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 },
930 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP },
931 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP },
932 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP },
933 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP },
934 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP },
935 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP },
936 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP },
937 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP },
938 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 },
939 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 },
940 { "adds/su", FP(0x16,0x580), BASE, ARG_FP },
941 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */
942 { "subs/su", FP(0x16,0x581), BASE, ARG_FP },
943 { "muls/su", FP(0x16,0x582), BASE, ARG_FP },
944 { "divs/su", FP(0x16,0x583), BASE, ARG_FP },
945 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP },
946 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */
947 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP },
948 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP },
949 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP },
950 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP },
951 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP },
952 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP },
953 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP },
954 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 },
955 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 },
956 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP },
957 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP },
958 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP },
959 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP },
960 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP },
961 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP },
962 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP },
963 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP },
964 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 },
965 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 },
966 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 },
967 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP },
968 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP },
969 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP },
970 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP },
971 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP },
972 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP },
973 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP },
974 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP },
975 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 },
976 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 },
977 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 },
978 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 },
979 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP },
980 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP },
981 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP },
982 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP },
983 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP },
984 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP },
985 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP },
986 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP },
987 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 },
988 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 },
989 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 },
990 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 },
991 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP },
992 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */
993 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP },
994 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP },
995 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP },
996 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP },
997 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */
998 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP },
999 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP },
1000 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP },
1001 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1002 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1003 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1004 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1005 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP },
1006 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP },
1007 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP },
1008 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP },
1009 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP },
1010 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP },
1011 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP },
1012 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP },
1013 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1014 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1015 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1016 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1017
1018 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 },
1019 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1020 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1021 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */
1022 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1023 { "cpys", FP(0x17,0x020), BASE, ARG_FP },
1024 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1025 { "cpysn", FP(0x17,0x021), BASE, ARG_FP },
1026 { "cpyse", FP(0x17,0x022), BASE, ARG_FP },
1027 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1028 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1029 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP },
1030 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP },
1031 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP },
1032 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP },
1033 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP },
1034 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP },
1035 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 },
1036 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 },
1037 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 },
1038
1039 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE },
1040 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */
1041 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE },
1042 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE },
1043 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
1044 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
1045 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
1046 { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } },
1047 { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */
1048 { "rc", MFC(0x18,0xE000), BASE, { RA } },
1049 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
1050 { "rs", MFC(0x18,0xF000), BASE, { RA } },
1051 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
1052 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
1053
1054 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1055 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1056 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1057 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1058 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1059 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1060 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1061 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1062 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1063 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1064 { "pal19", PCD(0x19), BASE, ARG_PCD },
1065
1066 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */
1067 BASE, { ZA, CPRB } },
1068 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1069 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1070 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1071 0xFFFFFFFF, BASE, { 0 } },
1072 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1073 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1074 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1075
1076 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1077 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1078 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1079 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1080 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1081 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1082 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1083 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1084 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1085 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1086 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1087 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1088 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1089 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1090 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1091 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1092 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1093 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1094 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1095 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1096 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1097 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1098 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1099 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1100 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1101 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1102 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1103 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1104 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1105 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1106 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1107 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1108 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1109 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1110 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1111 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1112 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1113 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1114 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1115 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1116 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1117 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1118 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1119 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1120 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1121 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1122 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1123 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1124 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1125 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1126 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1127 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1128 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1129 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1130 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1131 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1132 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1133 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1134 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1135 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1136 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1137 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1138 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1139 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1140 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1141 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1142 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1143 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1144 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1145 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1146 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1147 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1148 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1149 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1150 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1151 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1152 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1153 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1154 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1155 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1156 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1157 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1158 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1159 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1160 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1161 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1162 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1163 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1164 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1165 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1166 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1167 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1168 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1169 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1170 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1171 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1172 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1173 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1174 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1175 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1176 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1177 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1178 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1179 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1180 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1181 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1182 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1183 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1184 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1185 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1186 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1187 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1188 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1189 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1190 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1191 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1192 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1193 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1194 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1195 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1196 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1197 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1198 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1199 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1200 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1201 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1202 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1203 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1204 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1205 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1206 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1207 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1208 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1209 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1210 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1211 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1212 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1213 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1214 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1215 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1216 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1217 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1218 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1219 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1220 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1221 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1222 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1223 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1224 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1225 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1226 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1227 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1228 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1229 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1230 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1231 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1232 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1233 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1234 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1235 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1236 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1237 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1238 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1239 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1240 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1241 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1242 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1243 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1244 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1245 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1246 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1247 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1248 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1249 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1250 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1251 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1252 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1253 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1254 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1255 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1256 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1257 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1258 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1259 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1260 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1261 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1262 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1263 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1264 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1265 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1266 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1267 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1268 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1269 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1270 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1271 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1272 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1273 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1274 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1275 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1276 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1277 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1278 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1279 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1280 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1281 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1282 { "pal1b", PCD(0x1B), BASE, ARG_PCD },
1283
1284 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1285 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1286 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1287 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR },
1288 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1289 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1290 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1291 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1292 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1293 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1294 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR },
1295 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1296 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR },
1297 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1298 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR },
1299 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1300 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR },
1301 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1302 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR },
1303 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1304 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR },
1305 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1306 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR },
1307 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1308 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR },
1309 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1310 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1311 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1312
1313 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1314 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1315 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1316 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1317 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1318 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1319 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1320 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1321 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1322 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1323 { "pal1d", PCD(0x1D), BASE, ARG_PCD },
1324
1325 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1326 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1327 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1328 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1329 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1330 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1331 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1332 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1333 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1334 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1335 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1336 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1337 { "pal1e", PCD(0x1E), BASE, ARG_PCD },
1338
1339 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1340 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1341 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1342 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1343 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1344 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1345 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1346 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1347 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1348 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1349 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1350 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1351 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1352 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1353 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1354 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1355 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1356 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1357 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1358 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1359 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1360 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1361 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1362 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1363 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1364 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1365 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1366 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1367 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1368 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1369 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1370 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1371 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1372 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1373 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1374 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1375 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1376 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1377 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1378 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1379 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1380 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1381 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1382 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1383 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1384 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1385 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1386 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1387 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1388 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1389 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1390 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1391 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1392 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1393 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1394 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1395 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1396 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1397 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1398 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1399 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1400 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1401 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1402 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1403 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1404 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1405 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1406 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1407 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1408 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1409 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1410 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1411 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1412 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1413 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1414 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1415 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1416 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1417 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1418 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1419 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1420 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1421 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1422 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1423 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1424 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1425 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1426 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1427 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1428 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1429 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1430 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1431 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1432 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1433 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1434 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1435 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1436 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1437 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1438 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1439 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1440 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1441 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1442 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1443 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1444 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1445 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1446 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1447 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1448 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1449 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1450 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1451 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1452 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1453 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1454 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1455 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1456 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1457 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1458 { "pal1f", PCD(0x1F), BASE, ARG_PCD },
1459
1460 { "ldf", MEM(0x20), BASE, ARG_FMEM },
1461 { "ldg", MEM(0x21), BASE, ARG_FMEM },
1462 { "lds", MEM(0x22), BASE, ARG_FMEM },
1463 { "ldt", MEM(0x23), BASE, ARG_FMEM },
1464 { "stf", MEM(0x24), BASE, ARG_FMEM },
1465 { "stg", MEM(0x25), BASE, ARG_FMEM },
1466 { "sts", MEM(0x26), BASE, ARG_FMEM },
1467 { "stt", MEM(0x27), BASE, ARG_FMEM },
1468
1469 { "ldl", MEM(0x28), BASE, ARG_MEM },
1470 { "ldq", MEM(0x29), BASE, ARG_MEM },
1471 { "ldl_l", MEM(0x2A), BASE, ARG_MEM },
1472 { "ldq_l", MEM(0x2B), BASE, ARG_MEM },
1473 { "stl", MEM(0x2C), BASE, ARG_MEM },
1474 { "stq", MEM(0x2D), BASE, ARG_MEM },
1475 { "stl_c", MEM(0x2E), BASE, ARG_MEM },
1476 { "stq_c", MEM(0x2F), BASE, ARG_MEM },
1477
1478 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */
1479 { "br", BRA(0x30), BASE, ARG_BRA },
1480 { "fbeq", BRA(0x31), BASE, ARG_FBRA },
1481 { "fblt", BRA(0x32), BASE, ARG_FBRA },
1482 { "fble", BRA(0x33), BASE, ARG_FBRA },
1483 { "bsr", BRA(0x34), BASE, ARG_BRA },
1484 { "fbne", BRA(0x35), BASE, ARG_FBRA },
1485 { "fbge", BRA(0x36), BASE, ARG_FBRA },
1486 { "fbgt", BRA(0x37), BASE, ARG_FBRA },
1487 { "blbc", BRA(0x38), BASE, ARG_BRA },
1488 { "beq", BRA(0x39), BASE, ARG_BRA },
1489 { "blt", BRA(0x3A), BASE, ARG_BRA },
1490 { "ble", BRA(0x3B), BASE, ARG_BRA },
1491 { "blbs", BRA(0x3C), BASE, ARG_BRA },
1492 { "bne", BRA(0x3D), BASE, ARG_BRA },
1493 { "bge", BRA(0x3E), BASE, ARG_BRA },
1494 { "bgt", BRA(0x3F), BASE, ARG_BRA },
1495 };
1496
1497 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1498