1 /* s390-opc.c -- S390 opcode list 2 Copyright (C) 2000-2016 Free Software Foundation, Inc. 3 Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include <stdio.h> 23 #include "ansidecl.h" 24 #include "opcode/s390.h" 25 26 /* This file holds the S390 opcode table. The opcode table 27 includes almost all of the extended instruction mnemonics. This 28 permits the disassembler to use them, and simplifies the assembler 29 logic, at the cost of increasing the table size. The table is 30 strictly constant data, so the compiler should be able to put it in 31 the .text section. 32 33 This file also holds the operand table. All knowledge about 34 inserting operands into instructions and vice-versa is kept in this 35 file. */ 36 37 /* The operands table. 38 The fields are bits, shift, insert, extract, flags. */ 39 40 const struct s390_operand s390_operands[] = 41 { 42 #define UNUSED 0 43 { 0, 0, 0 }, /* Indicates the end of the operand list */ 44 45 /* General purpose register operands. */ 46 47 #define R_8 1 /* GPR starting at position 8 */ 48 { 4, 8, S390_OPERAND_GPR }, 49 #define R_12 2 /* GPR starting at position 12 */ 50 { 4, 12, S390_OPERAND_GPR }, 51 #define R_16 3 /* GPR starting at position 16 */ 52 { 4, 16, S390_OPERAND_GPR }, 53 #define R_20 4 /* GPR starting at position 20 */ 54 { 4, 20, S390_OPERAND_GPR }, 55 #define R_24 5 /* GPR starting at position 24 */ 56 { 4, 24, S390_OPERAND_GPR }, 57 #define R_28 6 /* GPR starting at position 28 */ 58 { 4, 28, S390_OPERAND_GPR }, 59 #define R_32 7 /* GPR starting at position 32 */ 60 { 4, 32, S390_OPERAND_GPR }, 61 62 /* General purpose register pair operands. */ 63 64 #define RE_8 8 /* GPR starting at position 8 */ 65 { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 66 #define RE_12 9 /* GPR starting at position 12 */ 67 { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 68 #define RE_16 10 /* GPR starting at position 16 */ 69 { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 70 #define RE_20 11 /* GPR starting at position 20 */ 71 { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 72 #define RE_24 12 /* GPR starting at position 24 */ 73 { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 74 #define RE_28 13 /* GPR starting at position 28 */ 75 { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 76 #define RE_32 14 /* GPR starting at position 32 */ 77 { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, 78 79 /* Floating point register operands. */ 80 81 #define F_8 15 /* FPR starting at position 8 */ 82 { 4, 8, S390_OPERAND_FPR }, 83 #define F_12 16 /* FPR starting at position 12 */ 84 { 4, 12, S390_OPERAND_FPR }, 85 #define F_16 17 /* FPR starting at position 16 */ 86 { 4, 16, S390_OPERAND_FPR }, 87 #define F_24 18 /* FPR starting at position 24 */ 88 { 4, 24, S390_OPERAND_FPR }, 89 #define F_28 19 /* FPR starting at position 28 */ 90 { 4, 28, S390_OPERAND_FPR }, 91 #define F_32 20 /* FPR starting at position 32 */ 92 { 4, 32, S390_OPERAND_FPR }, 93 94 /* Floating point register pair operands. */ 95 96 #define FE_8 21 /* FPR starting at position 8 */ 97 { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 98 #define FE_12 22 /* FPR starting at position 12 */ 99 { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 100 #define FE_16 23 /* FPR starting at position 16 */ 101 { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 102 #define FE_24 24 /* FPR starting at position 24 */ 103 { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 104 #define FE_28 25 /* FPR starting at position 28 */ 105 { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 106 #define FE_32 26 /* FPR starting at position 32 */ 107 { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, 108 109 /* Vector register operands. */ 110 111 /* For each of these operands and additional bit in the RXB operand is 112 needed. */ 113 114 #define V_8 27 /* Vector reg. starting at position 8 */ 115 { 4, 8, S390_OPERAND_VR }, 116 #define V_12 28 /* Vector reg. starting at position 12 */ 117 { 4, 12, S390_OPERAND_VR }, 118 #define V_CP16_12 29 /* Vector reg. starting at position 12 */ 119 { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ 120 #define V_16 30 /* Vector reg. starting at position 16 */ 121 { 4, 16, S390_OPERAND_VR }, 122 #define V_32 31 /* Vector reg. starting at position 32 */ 123 { 4, 32, S390_OPERAND_VR }, 124 125 /* Access register operands. */ 126 127 #define A_8 32 /* Access reg. starting at position 8 */ 128 { 4, 8, S390_OPERAND_AR }, 129 #define A_12 33 /* Access reg. starting at position 12 */ 130 { 4, 12, S390_OPERAND_AR }, 131 #define A_24 34 /* Access reg. starting at position 24 */ 132 { 4, 24, S390_OPERAND_AR }, 133 #define A_28 35 /* Access reg. starting at position 28 */ 134 { 4, 28, S390_OPERAND_AR }, 135 136 /* Control register operands. */ 137 138 #define C_8 36 /* Control reg. starting at position 8 */ 139 { 4, 8, S390_OPERAND_CR }, 140 #define C_12 37 /* Control reg. starting at position 12 */ 141 { 4, 12, S390_OPERAND_CR }, 142 143 /* Base register operands. */ 144 145 #define B_16 38 /* Base register starting at position 16 */ 146 { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, 147 #define B_32 39 /* Base register starting at position 32 */ 148 { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, 149 150 #define X_12 40 /* Index register starting at position 12 */ 151 { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, 152 153 #define VX_12 41 /* Vector index register starting at position 12 */ 154 { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, 155 156 /* Address displacement operands. */ 157 158 #define D_20 42 /* Displacement starting at position 20 */ 159 { 12, 20, S390_OPERAND_DISP }, 160 #define D_36 43 /* Displacement starting at position 36 */ 161 { 12, 36, S390_OPERAND_DISP }, 162 #define D20_20 44 /* 20 bit displacement starting at 20 */ 163 { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, 164 165 /* Length operands. */ 166 167 #define L4_8 45 /* 4 bit length starting at position 8 */ 168 { 4, 8, S390_OPERAND_LENGTH }, 169 #define L4_12 46 /* 4 bit length starting at position 12 */ 170 { 4, 12, S390_OPERAND_LENGTH }, 171 #define L8_8 47 /* 8 bit length starting at position 8 */ 172 { 8, 8, S390_OPERAND_LENGTH }, 173 174 /* Signed immediate operands. */ 175 176 #define I8_8 48 /* 8 bit signed value starting at 8 */ 177 { 8, 8, S390_OPERAND_SIGNED }, 178 #define I8_32 49 /* 8 bit signed value starting at 32 */ 179 { 8, 32, S390_OPERAND_SIGNED }, 180 #define I12_12 50 /* 12 bit signed value starting at 12 */ 181 { 12, 12, S390_OPERAND_SIGNED }, 182 #define I16_16 51 /* 16 bit signed value starting at 16 */ 183 { 16, 16, S390_OPERAND_SIGNED }, 184 #define I16_32 52 /* 16 bit signed value starting at 32 */ 185 { 16, 32, S390_OPERAND_SIGNED }, 186 #define I24_24 53 /* 24 bit signed value starting at 24 */ 187 { 24, 24, S390_OPERAND_SIGNED }, 188 #define I32_16 54 /* 32 bit signed value starting at 16 */ 189 { 32, 16, S390_OPERAND_SIGNED }, 190 191 /* Unsigned immediate operands. */ 192 193 #define U4_8 55 /* 4 bit unsigned value starting at 8 */ 194 { 4, 8, 0 }, 195 #define U4_12 56 /* 4 bit unsigned value starting at 12 */ 196 { 4, 12, 0 }, 197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ 198 { 4, 16, 0 }, 199 #define U4_20 58 /* 4 bit unsigned value starting at 20 */ 200 { 4, 20, 0 }, 201 #define U4_24 59 /* 4 bit unsigned value starting at 24 */ 202 { 4, 24, 0 }, 203 #define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */ 204 { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ 205 #define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */ 206 { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ 207 #define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */ 208 { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ 209 #define U4_28 63 /* 4 bit unsigned value starting at 28 */ 210 { 4, 28, 0 }, 211 #define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */ 212 { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ 213 #define U4_32 65 /* 4 bit unsigned value starting at 32 */ 214 { 4, 32, 0 }, 215 #define U4_36 66 /* 4 bit unsigned value starting at 36 */ 216 { 4, 36, 0 }, 217 #define U8_8 67 /* 8 bit unsigned value starting at 8 */ 218 { 8, 8, 0 }, 219 #define U8_16 68 /* 8 bit unsigned value starting at 16 */ 220 { 8, 16, 0 }, 221 #define U8_24 69 /* 8 bit unsigned value starting at 24 */ 222 { 8, 24, 0 }, 223 #define U8_32 70 /* 8 bit unsigned value starting at 32 */ 224 { 8, 32, 0 }, 225 #define U12_16 71 /* 12 bit unsigned value starting at 16 */ 226 { 12, 16, 0 }, 227 #define U16_16 72 /* 16 bit unsigned value starting at 16 */ 228 { 16, 16, 0 }, 229 #define U16_32 73 /* 16 bit unsigned value starting at 32 */ 230 { 16, 32, 0 }, 231 #define U32_16 74 /* 32 bit unsigned value starting at 16 */ 232 { 32, 16, 0 }, 233 234 /* PC-relative address operands. */ 235 236 #define J12_12 75 /* 12 bit PC relative offset at 12 */ 237 { 12, 12, S390_OPERAND_PCREL }, 238 #define J16_16 76 /* 16 bit PC relative offset at 16 */ 239 { 16, 16, S390_OPERAND_PCREL }, 240 #define J16_32 77 /* 16 bit PC relative offset at 32 */ 241 { 16, 32, S390_OPERAND_PCREL }, 242 #define J24_24 78 /* 24 bit PC relative offset at 24 */ 243 { 24, 24, S390_OPERAND_PCREL }, 244 #define J32_16 79 /* 32 bit PC relative offset at 16 */ 245 { 32, 16, S390_OPERAND_PCREL }, 246 247 }; 248 249 250 /* Macros used to form opcodes. */ 251 252 /* 8/16/48 bit opcodes. */ 253 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } 254 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } 255 #define OP32(x) { x >> 24, (x >> 16) & 255, (x >> 8) & 255, x & 255, \ 256 0x00, 0x00 } 257 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ 258 (x >> 16) & 255, (x >> 8) & 255, x & 255} 259 260 /* The new format of the INSTR_x_y and MASK_x_y defines is based 261 on the following rules: 262 1) the middle part of the definition (x in INSTR_x_y) is the official 263 names of the instruction format that you can find in the principals 264 of operation. 265 2) the last part of the definition (y in INSTR_x_y) gives you an idea 266 which operands the binary represenation of the instruction has. 267 The meanings of the letters in y are: 268 a - access register 269 c - control register 270 d - displacement, 12 bit 271 f - floating pointer register 272 fe - fpr extended operand, a valid floating pointer register pair 273 i - signed integer, 4, 8, 16 or 32 bit 274 l - length, 4 or 8 bit 275 p - pc relative 276 r - general purpose register 277 re - gpr extended operand, a valid general purpose register pair 278 u - unsigned integer, 4, 8, 16 or 32 bit 279 m - mode field, 4 bit 280 0 - operand skipped. 281 The order of the letters reflects the layout of the format in 282 storage and not the order of the paramaters of the instructions. 283 The use of the letters is not a 100% match with the PoP but it is 284 quite close. 285 286 For example the instruction "mvo" is defined in the PoP as follows: 287 288 MVO D1(L1,B1),D2(L2,B2) [SS] 289 290 -------------------------------------- 291 | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | 292 -------------------------------------- 293 0 8 12 16 20 32 36 294 295 The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ 296 297 #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ 298 #define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ 299 #define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ 300 #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ 301 #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ 302 #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ 303 #define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ 304 #define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ 305 #define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ 306 #define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ 307 #define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ 308 #define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ 309 #define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ 310 #define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ 311 #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ 312 #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ 313 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ 314 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ 315 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ 316 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ 317 #define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ 318 #define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ 319 #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ 320 #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ 321 #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ 322 #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ 323 #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ 324 #define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ 325 #define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ 326 #define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ 327 #define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ 328 #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ 329 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ 330 #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ 331 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ 332 #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ 333 #define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ 334 #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ 335 #define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ 336 #define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ 337 #define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ 338 #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ 339 #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ 340 #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ 341 #define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ 342 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ 343 #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ 344 #define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ 345 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ 346 #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ 347 #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ 348 #define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ 349 #define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ 350 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ 351 #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ 352 #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 353 #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ 354 #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ 355 #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ 356 #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 357 #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ 358 #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ 359 #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ 360 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ 361 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ 362 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ 363 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ 364 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 365 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ 366 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ 367 #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 368 #define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ 369 #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ 370 #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ 371 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ 372 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ 373 #define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ 374 #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ 375 #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ 376 #define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ 377 #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ 378 #define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ 379 #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ 380 #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ 381 #define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ 382 #define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ 383 #define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ 384 #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ 385 #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ 386 #define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ 387 #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ 388 #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ 389 #define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ 390 #define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ 391 #define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ 392 #define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ 393 #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 394 #define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ 395 #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ 396 #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 397 #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ 398 #define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ 399 #define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ 400 #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ 401 #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 402 #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ 403 #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 404 #define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ 405 #define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ 406 #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 407 #define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ 408 #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 409 #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 410 #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ 411 #define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ 412 #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ 413 #define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ 414 #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ 415 #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ 416 #define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ 417 #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ 418 #define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ 419 #define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ 420 #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ 421 #define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ 422 #define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ 423 #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ 424 #define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ 425 #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ 426 #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ 427 #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ 428 #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ 429 #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ 430 #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ 431 #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ 432 #define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ 433 #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ 434 #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ 435 #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ 436 #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ 437 #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ 438 #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ 439 #define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ 440 #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ 441 #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ 442 #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ 443 #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ 444 #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ 445 #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ 446 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ 447 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ 448 #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ 449 #define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ 450 #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ 451 #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ 452 #define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ 453 #define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ 454 #define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ 455 #define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ 456 #define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ 457 #define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ 458 #define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ 459 #define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ 460 #define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ 461 #define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ 462 #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ 463 #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ 464 #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ 465 #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ 466 #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ 467 #define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */ 468 #define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ 469 #define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ 470 #define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ 471 #define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ 472 #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ 473 #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ 474 #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ 475 #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ 476 #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ 477 #define INSTR_VRR_VVV0U1 6, { V_8,V_12,V_16,U4_OR1_24,0,0 } /* e.g. vfaebs*/ 478 #define INSTR_VRR_VVV0U2 6, { V_8,V_12,V_16,U4_OR2_24,0,0 } /* e.g. vfaezb*/ 479 #define INSTR_VRR_VVV0U3 6, { V_8,V_12,V_16,U4_OR3_24,0,0 } /* e.g. vfaezbs*/ 480 #define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ 481 #define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ 482 #define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ 483 #define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ 484 #define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ 485 #define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ 486 #define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */ 487 #define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ 488 #define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ 489 #define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ 490 #define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ 491 #define INSTR_VRR_VVVU0VB1 6, { V_8,V_12,V_16,V_32,U4_OR1_24,0 } /* e.g. vstrcbs*/ 492 #define INSTR_VRR_VVVU0VB2 6, { V_8,V_12,V_16,V_32,U4_OR2_24,0 } /* e.g. vstrczb*/ 493 #define INSTR_VRR_VVVU0VB3 6, { V_8,V_12,V_16,V_32,U4_OR3_24,0 } /* e.g. vstrczbs*/ 494 #define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ 495 #define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ 496 #define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ 497 #define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ 498 #define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ 499 #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ 500 #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ 501 #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ 502 503 #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 504 #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 505 #define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 506 #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 507 #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 508 #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 509 #define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 510 #define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 511 #define MASK_RIE_R0PI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 512 #define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 513 #define MASK_RIE_R0PU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 514 #define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } 515 #define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } 516 #define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } 517 #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } 518 #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 519 #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 520 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 521 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 522 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 523 #define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 524 #define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 525 #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 526 #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 527 #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 528 #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 529 #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 530 #define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 531 #define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 532 #define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 533 #define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 534 #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 535 #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } 536 #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 537 #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 538 #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 539 #define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 540 #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 541 #define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 542 #define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 543 #define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 544 #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 545 #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 546 #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 547 #define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 548 #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 549 #define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 550 #define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 551 #define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 552 #define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 553 #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 554 #define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 555 #define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 556 #define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 557 #define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 558 #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 559 #define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 560 #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 561 #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 562 #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 563 #define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 564 #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 565 #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 566 #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 567 #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 568 #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 569 #define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 570 #define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 571 #define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 572 #define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 573 #define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } 574 #define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } 575 #define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 576 #define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 577 #define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 578 #define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 579 #define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 580 #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 581 #define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 582 #define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 583 #define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 584 #define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 585 #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 586 #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 587 #define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 588 #define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 589 #define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 590 #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 591 #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 592 #define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 593 #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 594 #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 595 #define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 596 #define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 597 #define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 598 #define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 599 #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 600 #define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 601 #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 602 #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 603 #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } 604 #define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 605 #define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 606 #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 607 #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 608 #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 609 #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 610 #define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 611 #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 612 #define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 613 #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 614 #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 615 #define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 616 #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 617 #define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 618 #define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 619 #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 620 #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 621 #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 622 #define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 623 #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 624 #define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 625 #define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } 626 #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 627 #define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 628 #define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 629 #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } 630 #define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 631 #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 632 #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 633 #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 634 #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 635 #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 636 #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 637 #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 638 #define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 639 #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 640 #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 641 #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 642 #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 643 #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 644 #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 645 #define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 646 #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 647 #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 648 #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 649 #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 650 #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 651 #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 652 #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 653 #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 654 #define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 655 #define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 656 #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 657 #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 658 #define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 659 #define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } 660 #define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } 661 #define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 662 #define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } 663 #define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 664 #define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 665 #define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } 666 #define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } 667 #define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } 668 #define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } 669 #define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } 670 #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 671 #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 672 #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } 673 #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 674 #define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 675 #define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 676 #define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 677 #define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 678 #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 679 #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } 680 #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } 681 #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } 682 #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } 683 #define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } 684 #define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } 685 #define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } 686 #define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } 687 #define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } 688 #define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } 689 #define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } 690 #define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } 691 #define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } 692 #define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } 693 #define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } 694 #define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } 695 #define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } 696 #define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } 697 #define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } 698 #define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } 699 #define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } 700 #define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } 701 #define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } 702 #define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } 703 #define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } 704 #define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } 705 #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } 706 #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } 707 #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } 708 709 /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ 710 711 const struct s390_opcode s390_opformats[] = 712 { 713 { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, 714 { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, 715 { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, 716 { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, 717 { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, 718 { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 }, 719 { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, 720 { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, 721 { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, 722 { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 }, 723 { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, 724 { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, 725 { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, 726 { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, 727 { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, 728 { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, 729 { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 }, 730 { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, 731 { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, 732 { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, 733 { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, 734 { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, 735 { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 }, 736 { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, 737 { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 }, 738 }; 739 740 const int s390_num_opformats = 741 sizeof (s390_opformats) / sizeof (s390_opformats[0]); 742 743 #include "s390-opc.tab" 744