217           Sub(Op.getSubReg()) {}  in RegisterRef()
218       RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}  in RegisterRef()
220         return Reg == RR.Reg && Sub == RR.Sub;  in operator ==()
224         return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);  in operator <()
226       unsigned Reg, Sub;  member
232     unsigned getMaskForSub(unsigned Sub);
234     LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
289 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {  in INITIALIZE_PASS_DEPENDENCY()
290   switch (Sub) {  in INITIALIZE_PASS_DEPENDENCY()
316 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {  in getLaneMask()  argument
318   return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)  in getLaneMask()
325   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in addRefToMap()
339   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in isRefInMap()
522       MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);  in updateDeadsInRange()
591     unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);  in getCondTfrOpcode()
775       if (RR.Sub == RD.Sub)  in getReachingDefForPred()
777       if (RR.Sub == 0 || RD.Sub == 0)  in getReachingDefForPred()
933       Op.setSubReg(RN.Sub);  in renameInRange()
1107     BW = (RR.Sub != 0) ? 32 : 64;  in isIntReg()
1148                << PrintReg(R1.Reg, TRI, R1.Sub) << "  " << L1 << "\n  "  in coalesceRegisters()
1149                << PrintReg(R2.Reg, TRI, R2.Sub) << "  " << L2 << "\n");  in coalesceRegisters()
1150   if (R1.Sub || R2.Sub)  in coalesceRegisters()