43 			     struct radeon_winsys_cs *cs,  in radeon_cs_memory_below_limit()  argument
46 	vram += cs->used_vram;  in radeon_cs_memory_below_limit()
47 	gtt += cs->used_gart;  in radeon_cs_memory_below_limit()
75 		ring->cs, rbo->buf,  in radeon_add_to_buffer_list()
106 	    !radeon_cs_memory_below_limit(rctx->screen, ring->cs,  in radeon_add_to_buffer_list_check_mem()
114 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned nu…  in radeon_set_config_reg_seq()  argument
117 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);  in radeon_set_config_reg_seq()
118 	radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));  in radeon_set_config_reg_seq()
119 	radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);  in radeon_set_config_reg_seq()
122 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)  in radeon_set_config_reg()  argument
124 	radeon_set_config_reg_seq(cs, reg, 1);  in radeon_set_config_reg()
125 	radeon_emit(cs, value);  in radeon_set_config_reg()
128 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n…  in radeon_set_context_reg_seq()  argument
131 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);  in radeon_set_context_reg_seq()
132 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));  in radeon_set_context_reg_seq()
133 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_seq()
136 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)  in radeon_set_context_reg()  argument
138 	radeon_set_context_reg_seq(cs, reg, 1);  in radeon_set_context_reg()
139 	radeon_emit(cs, value);  in radeon_set_context_reg()
142 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,  in radeon_set_context_reg_idx()  argument
147 	assert(cs->current.cdw + 3 <= cs->current.max_dw);  in radeon_set_context_reg_idx()
148 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));  in radeon_set_context_reg_idx()
149 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_context_reg_idx()
150 	radeon_emit(cs, value);  in radeon_set_context_reg_idx()
153 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)  in radeon_set_sh_reg_seq()  argument
156 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);  in radeon_set_sh_reg_seq()
157 	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));  in radeon_set_sh_reg_seq()
158 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);  in radeon_set_sh_reg_seq()
161 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)  in radeon_set_sh_reg()  argument
163 	radeon_set_sh_reg_seq(cs, reg, 1);  in radeon_set_sh_reg()
164 	radeon_emit(cs, value);  in radeon_set_sh_reg()
167 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n…  in radeon_set_uconfig_reg_seq()  argument
170 	assert(cs->current.cdw + 2 + num <= cs->current.max_dw);  in radeon_set_uconfig_reg_seq()
171 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));  in radeon_set_uconfig_reg_seq()
172 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq()
175 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)  in radeon_set_uconfig_reg()  argument
177 	radeon_set_uconfig_reg_seq(cs, reg, 1);  in radeon_set_uconfig_reg()
178 	radeon_emit(cs, value);  in radeon_set_uconfig_reg()
181 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,  in radeon_set_uconfig_reg_idx()  argument
186 	assert(cs->current.cdw + 3 <= cs->current.max_dw);  in radeon_set_uconfig_reg_idx()
187 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));  in radeon_set_uconfig_reg_idx()
188 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_uconfig_reg_idx()
189 	radeon_emit(cs, value);  in radeon_set_uconfig_reg_idx()