1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * This file contains helpers for writing commands to commands streams.
26 */
27
28 #ifndef R600_CS_H
29 #define R600_CS_H
30
31 #include "radeonsi/si_pipe.h"
32 #include "amd/common/sid.h"
33
34 /**
35 * Return true if there is enough memory in VRAM and GTT for the buffers
36 * added so far.
37 *
38 * \param vram VRAM memory size not added to the buffer list yet
39 * \param gtt GTT memory size not added to the buffer list yet
40 */
41 static inline bool
radeon_cs_memory_below_limit(struct si_screen * screen,struct radeon_winsys_cs * cs,uint64_t vram,uint64_t gtt)42 radeon_cs_memory_below_limit(struct si_screen *screen,
43 struct radeon_winsys_cs *cs,
44 uint64_t vram, uint64_t gtt)
45 {
46 vram += cs->used_vram;
47 gtt += cs->used_gart;
48
49 /* Anything that goes above the VRAM size should go to GTT. */
50 if (vram > screen->info.vram_size)
51 gtt += vram - screen->info.vram_size;
52
53 /* Now we just need to check if we have enough GTT. */
54 return gtt < screen->info.gart_size * 0.7;
55 }
56
57 /**
58 * Add a buffer to the buffer list for the given command stream (CS).
59 *
60 * All buffers used by a CS must be added to the list. This tells the kernel
61 * driver which buffers are used by GPU commands. Other buffers can
62 * be swapped out (not accessible) during execution.
63 *
64 * The buffer list becomes empty after every context flush and must be
65 * rebuilt.
66 */
radeon_add_to_buffer_list(struct r600_common_context * rctx,struct r600_ring * ring,struct r600_resource * rbo,enum radeon_bo_usage usage,enum radeon_bo_priority priority)67 static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
68 struct r600_ring *ring,
69 struct r600_resource *rbo,
70 enum radeon_bo_usage usage,
71 enum radeon_bo_priority priority)
72 {
73 assert(usage);
74 return rctx->ws->cs_add_buffer(
75 ring->cs, rbo->buf,
76 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
77 rbo->domains, priority) * 4;
78 }
79
80 /**
81 * Same as above, but also checks memory usage and flushes the context
82 * accordingly.
83 *
84 * When this SHOULD NOT be used:
85 *
86 * - if r600_context_add_resource_size has been called for the buffer
87 * followed by *_need_cs_space for checking the memory usage
88 *
89 * - if r600_need_dma_space has been called for the buffer
90 *
91 * - when emitting state packets and draw packets (because preceding packets
92 * can't be re-emitted at that point)
93 *
94 * - if shader resource "enabled_mask" is not up-to-date or there is
95 * a different constraint disallowing a context flush
96 */
97 static inline unsigned
radeon_add_to_buffer_list_check_mem(struct r600_common_context * rctx,struct r600_ring * ring,struct r600_resource * rbo,enum radeon_bo_usage usage,enum radeon_bo_priority priority,bool check_mem)98 radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
99 struct r600_ring *ring,
100 struct r600_resource *rbo,
101 enum radeon_bo_usage usage,
102 enum radeon_bo_priority priority,
103 bool check_mem)
104 {
105 if (check_mem &&
106 !radeon_cs_memory_below_limit(rctx->screen, ring->cs,
107 rctx->vram + rbo->vram_usage,
108 rctx->gtt + rbo->gart_usage))
109 ring->flush(rctx, PIPE_FLUSH_ASYNC, NULL);
110
111 return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
112 }
113
radeon_set_config_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)114 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
115 {
116 assert(reg < SI_CONTEXT_REG_OFFSET);
117 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
118 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
119 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
120 }
121
radeon_set_config_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)122 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
123 {
124 radeon_set_config_reg_seq(cs, reg, 1);
125 radeon_emit(cs, value);
126 }
127
radeon_set_context_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)128 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
129 {
130 assert(reg >= SI_CONTEXT_REG_OFFSET);
131 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
132 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
133 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
134 }
135
radeon_set_context_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)136 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
137 {
138 radeon_set_context_reg_seq(cs, reg, 1);
139 radeon_emit(cs, value);
140 }
141
radeon_set_context_reg_idx(struct radeon_winsys_cs * cs,unsigned reg,unsigned idx,unsigned value)142 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
143 unsigned reg, unsigned idx,
144 unsigned value)
145 {
146 assert(reg >= SI_CONTEXT_REG_OFFSET);
147 assert(cs->current.cdw + 3 <= cs->current.max_dw);
148 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
149 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
150 radeon_emit(cs, value);
151 }
152
radeon_set_sh_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)153 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
154 {
155 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
156 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
157 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
158 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
159 }
160
radeon_set_sh_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)161 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
162 {
163 radeon_set_sh_reg_seq(cs, reg, 1);
164 radeon_emit(cs, value);
165 }
166
radeon_set_uconfig_reg_seq(struct radeon_winsys_cs * cs,unsigned reg,unsigned num)167 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
168 {
169 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
170 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
171 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
172 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
173 }
174
radeon_set_uconfig_reg(struct radeon_winsys_cs * cs,unsigned reg,unsigned value)175 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
176 {
177 radeon_set_uconfig_reg_seq(cs, reg, 1);
178 radeon_emit(cs, value);
179 }
180
radeon_set_uconfig_reg_idx(struct radeon_winsys_cs * cs,unsigned reg,unsigned idx,unsigned value)181 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
182 unsigned reg, unsigned idx,
183 unsigned value)
184 {
185 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
186 assert(cs->current.cdw + 3 <= cs->current.max_dw);
187 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
188 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
189 radeon_emit(cs, value);
190 }
191
192 #endif
193