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Searched defs:ASR (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/AVR/
DAVRISelLowering.h40 ASR, ///< Arithmetic shift right. enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRISelLowering.h41 ASR, ///< Arithmetic shift right. enumerator
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h356 ASR, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h397 ASR, enumerator
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h36 ASR, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h36 ASR, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/
DFunctionComparator.cpp668 unsigned int ASR = GEPR->getPointerAddressSpace(); in cmpGEPs() local
/external/v8/src/arm/
Dconstants-arm.h239 ASR = 2 << 5, // Arithmetic shift right. enumerator
/external/llvm/lib/Transforms/IPO/
DMergeFunctions.cpp1073 unsigned int ASR = GEPR->getPointerAddressSpace(); in cmpGEPs() local
/external/vixl/src/aarch32/
Dinstructions-aarch32.h1051 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enumerator
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md82 ### ASR ### subsection
/external/v8/src/arm64/
Dconstants-arm64.h368 ASR = 0x2, enumerator
/external/vixl/src/aarch64/
Dconstants-aarch64.h284 ASR = 0x2, enumerator
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.cpp2799 const bool ASR = Op == InstArithmetic::Ashr; in lowerInt64Arithmetic() local