| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 123 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
131 unsigned DefIdx) const override { in hasLowDefLatency()
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| D | PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI]; in formWebs() local
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
771 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 128 unsigned DefIdx = 0; in findDefIdx() local
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| D | TargetInstrInfo.cpp | 982 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1070 unsigned DefIdx, in getOperandLatency()
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency()
1124 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1149 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1172 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| D | LiveRangeCalc.cpp | 46 SlotIndex DefIdx = in createDeadDef() local
195 unsigned DefIdx; in extendToUses() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 66 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency()
78 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 131 unsigned DefIdx; variable
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 141 unsigned DefIdx; variable
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 125 unsigned DefIdx; variable
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 164 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
184 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| D | MCSubtargetInfo.h | 129 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrItineraries.h | 199 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
220 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 182 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
203 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| D | MCSubtargetInfo.h | 130 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 178 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
186 unsigned DefIdx) const override { in hasLowDefLatency()
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| D | PPCVSXSwapRemoval.cpp | 624 int DefIdx = SwapMap[DefMI]; in formWebs() local
705 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
781 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 159 unsigned DefIdx = 0; in findDefIdx() local
219 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
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| D | TargetInstrInfo.cpp | 1041 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1129 unsigned DefIdx, in getOperandLatency()
1154 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1181 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1206 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| D | LiveRangeCalc.cpp | 68 SlotIndex DefIdx = in createDeadDef() local
199 unsigned DefIdx; in extendToUses() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 44 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3187 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3228 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3331 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
3442 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
3675 unsigned DefIdx, in getOperandLatency()
3711 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
3771 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4074 unsigned DefIdx, in hasHighOperandLatency()
4596 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
4621 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef() local
768 SlotIndex DefIdx = UseIdx.getDefIndex(); in RemoveCopyByCommutingDef() local
1016 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getDefIndex(); in RemoveDeadDef() local
1026 SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); in RemoveCopyFlag() local
1939 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getDefIndex(); in runOnMachineFunction() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 934 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
948 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3517 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3574 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3677 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
3788 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
4021 unsigned DefIdx, in getOperandLatency()
4057 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
4117 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4463 unsigned DefIdx, in hasHighOperandLatency()
4991 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
5018 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
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