| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1134 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1155 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1187 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1203 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1259 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1298 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1353 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1383 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
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| D | AArch64ISelLowering.cpp | 9229 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 495 unsigned NumVecs) { in createInterleaveMask()
553 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1076 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1191 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1218 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1250 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1271 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1327 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1366 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1421 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1451 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
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| D | AArch64ISelLowering.cpp | 10249 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1533 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs, in GetVLDSTAlign()
1552 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1676 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
1814 bool isUpdating, unsigned NumVecs, in SelectVLDSTLane()
1934 unsigned NumVecs, unsigned *Opcodes) { in SelectVLDDup()
2010 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
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| D | ARMISelLowering.cpp | 7176 unsigned NumVecs = 0; in CombineBaseUpdate() local
7293 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1603 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
1738 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
1743 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1881 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2034 unsigned NumVecs, in SelectVLDSTLane()
2160 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
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| D | ARMISelLowering.cpp | 11552 unsigned NumVecs = 0; in CombineBaseUpdate() local
11756 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1944 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2093 unsigned NumVecs, in SelectVLDSTLane()
2214 void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLDDup()
2296 void ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
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| D | ARMISelLowering.cpp | 9923 unsigned NumVecs = 0; in CombineBaseUpdate() local
10123 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 37753 unsigned NumVecs = VT.getSizeInBits() / SplitSize; in combineToExtendVectorInReg() local
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