| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 182 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
463 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
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| D | MipsISelLowering.cpp | 1543 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 334 unsigned ShiftImm; // shift for OffsetReg. member
344 unsigned ShiftImm; member
355 unsigned ShiftImm; member
360 unsigned ShiftImm; member
1508 unsigned ShiftImm, in CreateShiftedRegister()
1522 unsigned ShiftImm, in CreateShiftedImmediate()
1611 unsigned ShiftImm, in CreateMem()
1630 unsigned ShiftImm, in CreatePostIdxReg()
2716 unsigned ShiftImm = 0; in parsePostIdxReg() local
3246 unsigned ShiftImm = 0; in parseMemory() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 516 unsigned ShiftImm; // shift for OffsetReg. member
526 unsigned ShiftImm; member
538 unsigned ShiftImm; member
544 unsigned ShiftImm; member
2650 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister()
2664 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreateShiftedImmediate()
2805 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, in CreateMem()
2823 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreatePostIdxReg()
4667 unsigned ShiftImm = 0; in parsePostIdxReg() local
4993 unsigned ShiftImm = 0; in parseMemory() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 750 unsigned ShiftImm; // shift for OffsetReg. member
760 unsigned ShiftImm; member
772 unsigned ShiftImm; member
778 unsigned ShiftImm; member
2966 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister()
2980 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreateShiftedImmediate()
3121 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, in CreateMem()
3139 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreatePostIdxReg()
4878 unsigned ShiftImm = 0; in parsePostIdxReg() local
5206 unsigned ShiftImm = 0; in parseMemory() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1327 unsigned ShiftImm; in emitAddSub_ri() local
1368 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs()
1411 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx()
1568 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs()
1707 uint64_t ShiftImm) { in emitLogicalOp_rs()
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| D | AArch64ISelDAGToDAG.cpp | 1595 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1732 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1277 unsigned ShiftImm; in emitAddSub_ri() local
1318 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs()
1359 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx()
1514 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs()
1653 uint64_t ShiftImm) { in emitLogicalOp_rs()
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| D | AArch64ISelDAGToDAG.cpp | 1526 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1662 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 444 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1083 int64_t ShiftImm = (Size == 1) ? 24 : 16; in EmitAtomicBinaryPartword() local
1294 int64_t ShiftImm = (Size == 1) ? 24 : 16; in EmitAtomicCmpSwapPartword() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2787 unsigned ShiftImm; in SelectShift() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2759 unsigned ShiftImm; in SelectShift() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1218 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28900 if (auto *ShiftImm = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { in computeKnownBitsForTargetNode() local
34331 unsigned ShiftImm = ShiftVal.getZExtValue(); in combineVectorShiftImm() local
|