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/external/libchrome/mojo/core/ports/
Dnode.cc2 // Use of this source code is governed by a BSD-style license that can be
39 // Random port name generator which maintains a cache of random bytes to draw
41 // RandBytes may have significant per-call overhead.
44 // a process once any port names have been generated, as that behavior can lead
82 bool CanAcceptMoreMessages(const Port* port) { in CanAcceptMoreMessages() argument
85 uint64_t next_sequence_num = port->message_queue.next_sequence_num(); in CanAcceptMoreMessages()
86 if (port->state == Port::kClosed) in CanAcceptMoreMessages()
88 if (port->peer_closed || port->remove_proxy_on_last_message) { in CanAcceptMoreMessages()
89 if (port->last_sequence_num_to_receive == next_sequence_num - 1) in CanAcceptMoreMessages()
116 DVLOG(2) << "Port " << entry.first << " referencing node " in CanShutdownCleanly()
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Dport.h2 // Use of this source code is governed by a BSD-style license that can be
26 // A Port is essentially a node in a circular list of addresses. For the sake of
31 // Each Port is identified by a 128-bit address within a Node (see node.h). A
32 // Port doesn't really *do* anything per se: it's a named collection of state,
44 // +-----+ +-----+
45 // | |--------->| |
47 // | |<---------| |
48 // +-----+ +-----+
52 // to a given Port; it is only aware of where it must route events FROM a given
53 // Port.
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/external/selinux/libsepol/src/
Dport_record.c9 /* Low - High range. Same for single ports. */
20 /* Low - High range. Same for single ports. */
37 ERR(handle, "out of memory, could not create " "port key"); in sepol_port_key_create()
41 tmp_key->low = low; in sepol_port_key_create()
42 tmp_key->high = high; in sepol_port_key_create()
43 tmp_key->proto = proto; in sepol_port_key_create()
55 *low = key->low; in hidden_def()
56 *high = key->high; in hidden_def()
57 *proto = key->proto; in hidden_def()
63 const sepol_port_t * port, in hidden_def()
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Dports.c53 /* Create a low level port structure from
57 ocontext_t ** port, const sepol_port_t * data) in port_from_record() argument
76 tmp_port->u.port.protocol = tmp_proto; in port_from_record()
78 /* Port range */ in port_from_record()
79 tmp_port->u.port.low_port = low; in port_from_record()
80 tmp_port->u.port.high_port = high; in port_from_record()
81 if (tmp_port->u.port.low_port > tmp_port->u.port.high_port) { in port_from_record()
82 ERR(handle, "low port %d exceeds high port %d", in port_from_record()
83 tmp_port->u.port.low_port, tmp_port->u.port.high_port); in port_from_record()
91 context_cpy(&tmp_port->context[0], tmp_con); in port_from_record()
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/external/libevent/
Devent_iocp.c2 * Copyright (c) 2009-2012 Niels Provos, Nick Mathewson
26 #include "evconfig-private.h"
39 #include "util-internal.h"
40 #include "iocp-internal.h"
41 #include "log-internal.h"
42 #include "mm-internal.h"
43 #include "event-internal.h"
44 #include "evthread-internal.h"
46 #define NOTIFICATION_KEY ((ULONG_PTR)-1)
52 o->cb = cb; in event_overlapped_init_()
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/external/u-boot/arch/powerpc/cpu/mpc8xxx/
Dsrio.c1 // SPDX-License-Identifier: GPL-2.0+
44 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
51 * Erratum A-004034
53 * Description: During port initialization, the SRIO port performs
58 * the configured port width.
59 * An SRIO port configured as a 4x port may see one of these scenarios:
65 * An SRIO port configured as a 1x port may fail to complete port
67 * Impact: SRIO port may downtrain to 1x, or may fail to complete
68 * link initialization. Once a port completes link initialization
71 static int srio_erratum_a004034(u8 port) in srio_erratum_a004034() argument
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/external/u-boot/drivers/net/
Dmvpp2.c8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
38 /* Some linux -> U-Boot compatibility stuff */
81 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) argument
82 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) argument
87 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) argument
108 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) argument
109 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) argument
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Dvsc9953.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
19 .port[0] = VSC9953_PORT_INFO_INITIALIZER(0),
20 .port[1] = VSC9953_PORT_INFO_INITIALIZER(1),
21 .port[2] = VSC9953_PORT_INFO_INITIALIZER(2),
22 .port[3] = VSC9953_PORT_INFO_INITIALIZER(3),
23 .port[4] = VSC9953_PORT_INFO_INITIALIZER(4),
24 .port[5] = VSC9953_PORT_INFO_INITIALIZER(5),
25 .port[6] = VSC9953_PORT_INFO_INITIALIZER(6),
26 .port[7] = VSC9953_PORT_INFO_INITIALIZER(7),
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/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dfsl.ll6 ; RUN: llc -O3 < %s -march=mblaze | FileCheck %s
8 declare i32 @llvm.mblaze.fsl.get(i32 %port)
9 declare i32 @llvm.mblaze.fsl.aget(i32 %port)
10 declare i32 @llvm.mblaze.fsl.cget(i32 %port)
11 declare i32 @llvm.mblaze.fsl.caget(i32 %port)
12 declare i32 @llvm.mblaze.fsl.eget(i32 %port)
13 declare i32 @llvm.mblaze.fsl.eaget(i32 %port)
14 declare i32 @llvm.mblaze.fsl.ecget(i32 %port)
15 declare i32 @llvm.mblaze.fsl.ecaget(i32 %port)
16 declare i32 @llvm.mblaze.fsl.nget(i32 %port)
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/external/u-boot/drivers/serial/
Dserial_sh.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2002 - 2008 Paul Mundt
26 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
28 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
31 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
33 if ((port->mapbase == 0xffe00000) || in scif_rxfill()
34 (port->mapbase == 0xffe08000)) { in scif_rxfill()
36 return sci_in(port, SCRFDR) & 0xff; in scif_rxfill()
39 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; in scif_rxfill()
43 static int scif_rxfill(struct uart_port *port) in scif_rxfill() argument
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/external/u-boot/arch/x86/include/asm/arch-quark/
Dmsg_port.h1 /* SPDX-License-Identifier: GPL-2.0+ */
38 * msg_port_setup - set up the message port control register
41 * @port: port number on the message bus
42 * @reg: register number within a port
44 void msg_port_setup(int op, int port, int reg);
47 * msg_port_read - read a message port register using normal opcode
49 * @port: port number on the message bus
50 * @reg: register number within a port
52 * @return: message port register value
54 u32 msg_port_read(u8 port, u32 reg);
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/external/u-boot/arch/arm/cpu/arm926ejs/mx27/
Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
14 #include <asm/mach-imx/sys_proto.h>
23 * f = 2 * f_ref * --------------------
48 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
59 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
67 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
73 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
88 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
100 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
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/external/u-boot/drivers/ata/
Dsata_sil3114.c1 // SPDX-License-Identifier: GPL-2.0+
39 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE]; variable
43 while (words--) { in output_data()
44 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr); in output_data()
50 while (words--) { in input_data()
51 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr); in input_data()
60 port[num].dev_mask = 1; in sata_bus_softreset()
62 port[num].ctl_reg = 0x08; /*Default value of control reg */ in sata_bus_softreset()
63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
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/external/iproute2/man/man8/
Ddevlink-port.81 .TH DEVLINK\-PORT 8 "14 Mar 2016" "iproute2" "Linux"
3 devlink-port \- devlink port configuration
11 .B port
18 \fB\-V\fR[\fIersion\fR] |
19 \fB\-n\fR[\fIno-nice-names\fR] }
39 .B devlink port show
43 .B devlink port help
46 .SS devlink port set - change devlink port attributes
50 - specifies the devlink port to operate on.
59 set port type
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/external/tcpdump/tests/
Dmstp-v.out2 port-role Root, CIST root-id 0000.00:1f:27:b4:7d:80, CIST ext-pathcost 200000
3 CIST regional-root-id 8000.00:16:46:b5:8c:80, CIST port-id 8012,
4 message-age 1.00s, max-age 20.00s, hello-time 2.00s, forwarding-delay 15.00s
6 digest 9357ebb7a8d74dd5fef4f2bab50531aa, CIST int-root-pathcost 200000,
7 CIST bridge-id 8000.00:1e:f7:05:a8:80, CIST remaining-hops 20
8 MSTI 1, Flags [Learn, Forward, Agreement, Topology change ACK], port-role Designated
9 MSTI regional-root-id 6001.00:1e:f7:05:a8:80, pathcost 0
10 MSTI bridge-prio 6, port-prio 8, hops 20
11 MSTI 2, Flags [Learn, Forward, Agreement, Topology change ACK], port-role Root
12 MSTI regional-root-id 8002.00:16:46:b5:8c:80, pathcost 200000
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Dspb_bpduv4-v.out2 port-role Designated, CIST root-id 8000.52:54:00:45:5f:15, CIST ext-pathcost 0
3 CIST regional-root-id 8000.52:54:00:45:5f:15, CIST port-id 8003,
4 message-age 0.00s, max-age 20.00s, hello-time 2.00s, forwarding-delay 15.00s
6 digest 67d768dfa948eb5e9fd54077e80975a2, CIST int-root-pathcost 0,
7 CIST bridge-id 8000.52:54:00:45:5f:15, CIST remaining-hops 20
8 MSTI 10, Flags [Learn, Forward], port-role Designated
9 MSTI regional-root-id 800a.52:54:00:45:5f:15, pathcost 0
10 MSTI bridge-prio 8, port-prio 8, hops 20
13 Agreement num 0, Discarded Agreement num 0, Agreement valid-flag 0,
14 Restricted role-flag: 0, Format id 0 cap 0, Convention id 2 cap 32,
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/external/autotest/client/site_tests/usbpd_GFU/
Dusbpd_GFU.py2 # Use of this source code is governed by a BSD-style license that can be
17 """Integration test for USB-PD Google Firmware Update (GFU).
20 - interrogate what firmware's are available for each device and for each:
22 - Validate that kernel driver successfully updates to latest RW.
31 FW_PATH = '/lib/firmware/cros-pd'
32 # <device>_v<major>.<minor>.<build>-<commit SHA>
33 FW_NAME_RE = r'%s/(\w+)_v(\d+)\.(\d+)\.(\d+)-([0-9a-f]+).*' % (FW_PATH)
46 """Index the various USB-PD firmwares in the rootfs.
55 for fw in glob.glob('%s/*_v[1-9].*.bin' % (self.FW_PATH)):
65 def _is_gfu(self, port): argument
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/external/u-boot/arch/m68k/include/asm/
Dimmap_5445x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
89 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
91 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
92 u16 cir; /* Chip Identification Register (Read-only) */
96 u16 uocsr; /* USB On-the-Go Controller Status Register */
101 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
102 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
103 u8 podr_ssi; /* SSI Port Output Data Register */
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Dio.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
41 * The insw/outsw/insl/outsl macros don't do byte-swapping.
43 * are arrays of bytes, and byte-swapping is not appropriate in
44 * that case. - paulus
46 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
47 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) argument
48 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
49 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) argument
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/external/u-boot/drivers/bios_emulator/
Dbesys.c11 * Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
42 * Jason ported this file to u-boot to run the ATI video card
43 * BIOS in u-boot. Removed some emulate functions such as the
44 * timer port access. Made all the VGA port except reading 0x3c3
46 * 16 bit of the io port.
55 /*------------------------- Global Variables ------------------------------*/
71 /*----------------------------- Implementation ----------------------------*/
75 addr - Emulator memory address to convert
81 This function converts an emulator memory address in a 32-bit range to
89 return (u8*)(_BE_env.biosmem_base + addr - 0xC0000); in BE_memaddr()
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/external/guava/guava/src/com/google/common/net/
DHostAndPort.java8 * http://www.apache.org/licenses/LICENSE-2.0
34 * An immutable representation of a host and port.
52 * <li>[2001:db8::1] - {@link #getHostText()} omits brackets
53 * <li>[2001:db8::1]:80 - {@link #getHostText()} omits brackets
54 * <li>2001:db8::1 - Use {@link #requireBracketsForIPv6()} to prohibit this
58 * concerned with brackets, colons, and port numbers. Full validation of the
68 /** Magic value indicating the absence of a port number. */
69 private static final int NO_PORT = -1;
74 /** Validated port number in the range [0..65535], or NO_PORT */
75 private final int port; field in HostAndPort
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/external/adhd/scripts/
Dini_editor.py4 # Use of this source code is governed by a BSD-style license that can be
25 class Port(object): class
26 """Class for port definition in ini file.
30 index: an integer for port index.
31 definition: a string for the content after "=" in port definition line.
36 """Parses a port definition line in ini file and init a Port object.
39 line: A string possibly containing port definition line like
43 A Port object if input is a valid port definition line. Returns
44 None if input is not a valid port definition line.
52 return Port(io, index, definition)
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/external/u-boot/arch/powerpc/include/asm/
Diopin_8xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * MPC8xx I/O port pin manipulation functions
18 u_char port:2; /* port number (A=0, B=1, C=2, D=3) */ member
19 u_char pin:5; /* port pin (0-31) */
32 if (iopin->port == IOPIN_PORTA) { in iopin_set_high()
33 ushort __iomem *datp = &immap->im_ioport.iop_padat; in iopin_set_high()
35 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
36 } else if (iopin->port == IOPIN_PORTB) { in iopin_set_high()
37 uint __iomem *datp = &immap->im_cpm.cp_pbdat; in iopin_set_high()
39 setbits_be32(datp, 1 << (31 - iopin->pin)); in iopin_set_high()
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/external/u-boot/doc/
DREADME.t1040-l2switch6 VSC9953 is an 8-port Gigabit Ethernet switch supports the following features:
7 - 8192 MAC addresses
8 - Static Address provisioning
9 - Dynamic learning of MAC addresses and aging
10 - 4096 VLANs
11 - Independent and shared VLAN learning (IVL, SVL)
12 - Policing with storm control and MC/BC protection
13 - IPv4 and IPv6 multicast
14 - Jumbo frames (9.6 KB)
15 - Access Control List
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/external/python/cpython2/Demo/sockets/
Dgopher.py5 # Usage: gopher [ [selector] host [port] ]
12 # Default selector, host and port
36 # Oft-used characters and strings
40 # Open a TCP connection to a given host and port
41 def open_socket(host, port): argument
42 if not port:
43 port = DEF_PORT
44 elif type(port) == type(''):
45 port = string.atoi(port)
47 s.connect((host, port))
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