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Searched refs:cond_reg (Results 1 – 2 of 2) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_mips.cc6220 Register cond_reg = TMP; in GenConditionalMoveR2() local
6227 cond_reg = locations->InAt(/* at= */ 2).AsRegister<Register>(); in GenConditionalMoveR2()
6236 cond_inverted = MaterializeIntCompare(if_cond, cond_locations, cond_reg); in GenConditionalMoveR2()
6264 __ Movz(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6266 __ Movn(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6271 __ Movz(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6272 __ Movz(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_reg); in GenConditionalMoveR2()
6274 __ Movn(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6275 __ Movn(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_reg); in GenConditionalMoveR2()
6280 __ MovzS(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_reg); in GenConditionalMoveR2()
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Dcode_generator_mips64.cc4664 GpuRegister cond_reg = TMP; in GenConditionalMove() local
4671 cond_reg = locations->InAt(/* at= */ 2).AsRegister<GpuRegister>(); in GenConditionalMove()
4682 cond_reg); in GenConditionalMove()
4688 cond_reg); in GenConditionalMove()
4711 __ Mfc1(cond_reg, fcond_reg); in GenConditionalMove()
4715 __ Selnez(dst.AsRegister<GpuRegister>(), false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4717 __ Seleqz(dst.AsRegister<GpuRegister>(), false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4721 __ Seleqz(dst.AsRegister<GpuRegister>(), true_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4723 __ Selnez(dst.AsRegister<GpuRegister>(), true_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4726 DCHECK_NE(cond_reg, AT); in GenConditionalMove()
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