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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dlarge-vector.ll2 …iple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS
13 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #8
14 ; CHECK-AAPCS: vld1.64 {d0, d1}, [r[[BASE]]]
15 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #24
16 ; CHECK-AAPCS: vld1.64 {d2, d3}, [r[[BASE]]]
34 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #24
35 ; CHECK-AAPCS: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
36 ; CHECK-AAPCS: add r[[BASE:[0-9]+]], sp, #8
37 ; CHECK-AAPCS: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
Darm-abi-attr.ll1 ; RUN: llc -mtriple=arm-linux-gnu < %s | FileCheck %s --check-prefix=AAPCS
7 ; RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s --check-prefix=AAPCS
9 ; RUN: FileCheck %s --check-prefix=AAPCS
11 ; RUN: FileCheck %s --check-prefix=AAPCS
13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
20 ; AAPCS: sub sp, sp, #8
21 ; AAPCS-NOT: bic
Dtail-call.ll6 ; RUN: | FileCheck %s -check-prefix CHECK-TAIL-AAPCS -check-prefix CHECK
45 ; CHECK-TAIL-AAPCS: b variadic
56 ; CHECK-TAIL-AAPCS: b variadic
64 ; that %z is passed in r1-r2 if APCS is used, contrary to AAPCS where r2-r3
70 ; CHECK-TAIL-AAPCS: bl variadic
83 ; CHECK-TAIL-AAPCS: b variadic
D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
/external/llvm/test/CodeGen/ARM/
Darm-abi-attr.ll7 ; RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s --check-prefix=AAPCS
9 ; RUN: FileCheck %s --check-prefix=AAPCS
11 ; RUN: FileCheck %s --check-prefix=AAPCS
13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
20 ; AAPCS: sub sp, sp, #8
21 ; AAPCS-NOT: bic
D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll1 ;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules.
/external/llvm/test/CodeGen/AArch64/
Di1-contents.ll6 ; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
17 ; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
30 ; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
Dargument-blocks.ll2 …c -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS
44 ; CHECK-AAPCS: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp, #8]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Di1-contents.ll6 ; AAPCS: low 8 bits of %in (== w0) will be either 0 or 1. Need to extend to
17 ; AAPCS: low 8 bits of %val1 (== w0) will be either 0 or 1. Need to extend to
30 ; AAPCS: low 8 bits of w0 must be either 0 or 1. Need to mask them off.
Dargument-blocks.ll2 …c -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS
44 ; CHECK-AAPCS: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp, #8]
/external/llvm/test/CodeGen/ARM/Windows/
Daapcs.ll3 ; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/Windows/
Daapcs.ll3 ; AAPCS mandates an 8-byte stack alignment. The alloca is implicitly aligned,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.td106 // ARM AAPCS (EABI) Calling Convention, common parts
133 // ARM AAPCS (EABI) Calling Convention
157 // ARM AAPCS-VFP (EABI) Calling Convention
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dtail-call-r9.ll6 ; the destination address. It's callee-saved in AAPCS.
/external/llvm/test/CodeGen/Thumb2/
Dtail-call-r9.ll6 ; the destination address. It's callee-saved in AAPCS.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td122 // ARM AAPCS (EABI) Calling Convention, common parts
152 // ARM AAPCS (EABI) Calling Convention
195 // ARM AAPCS-VFP (EABI) Calling Convention
257 // pointer, we use this AAPCS alternative.
/external/llvm/lib/Target/ARM/
DARMCallingConv.td122 // ARM AAPCS (EABI) Calling Convention, common parts
152 // ARM AAPCS (EABI) Calling Convention
194 // ARM AAPCS-VFP (EABI) Calling Convention
252 // pointer, we use this AAPCS alternative.
/external/llvm/test/tools/llvm-readobj/ARM/
Dattribute-0.s163 @CHECK-OBJ-NEXT: Description: AAPCS
170 @CHECK-OBJ-NEXT: Description: AAPCS
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-readobj/ARM/
Dattribute-0.s163 @CHECK-OBJ-NEXT: Description: AAPCS
170 @CHECK-OBJ-NEXT: Description: AAPCS
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Ddirective-eabi_attribute.s163 @ CHECK-OBJ-NEXT: Description: AAPCS VFP
169 @ CHECK-OBJ-NEXT: Description: AAPCS
/external/llvm/test/MC/ARM/
Ddirective-eabi_attribute.s163 @ CHECK-OBJ-NEXT: Description: AAPCS VFP
169 @ CHECK-OBJ-NEXT: Description: AAPCS
/external/llvm/docs/
DBigEndianNEON.rst100 AAPCS section in Considerations
103 The ARM procedure call standard (AAPCS) defines the ABI for passing vectors between functions in re…
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DBigEndianNEON.rst100 AAPCS section in Considerations
103 The ARM procedure call standard (AAPCS) defines the ABI for passing vectors between functions in re…
147 | AAPCS | ``LDR`` | ``LD1 + REV`` |

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