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Searched refs:ADDI (Results 1 – 25 of 69) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dexpand-isel-8.mir46 $r4 = ADDI $r3, 1
58 ; CHECK: $r5 = ADDI $r3, 0
59 ; CHECK: $r3 = ADDI $r4, 0
60 ; CHECK: $r4 = ADDI $r3, 0
Dexpand-isel-1.mir45 $r5 = ADDI $r3, 1
52 ; CHECK: $r0 = ADDI $zero, 0
Dexpand-isel-5.mir45 $r5 = ADDI $r3, 1
51 ; CHECK: $r0 = ADDI $r5, 0
Dexpand-isel-6.mir46 $r5 = ADDI $r3, 1
54 ; CHECK: $r3 = ADDI $zero, 0
Dexpand-isel-2.mir46 $r5 = ADDI $r3, 1
54 ; CHECK: $r3 = ADDI $zero, 0
Dexpand-isel-7.mir46 $r4 = ADDI $r3, 1
54 ; CHECK: $r5 = ADDI $r3, 0
Dexpand-isel-3.mir46 $r5 = ADDI $r3, 1
54 ; CHECK: $r3 = ADDI $r4, 0
Dexpand-isel-10.mir45 $r5 = ADDI $r3, 1
49 ; CHECK: $r5 = ADDI $r3, 1
Dexpand-isel-4.mir47 $r5 = ADDI $r3, 1
55 ; CHECK: $r0 = ADDI killed $zero, 0
Dconvert-rr-to-ri-instrs.mir1054 ; CHECK: ADDI killed %3, 33
1055 ; CHECK: ADDI killed %4, 33
1341 %2 = ADDI killed %1, 44
2079 %3 = ADDI %2, 1
2084 %8 = ADDI %2, 2
2156 %3 = ADDI %2, 1
2163 %8 = ADDI %2, 2
2236 %3 = ADDI %2, 1
2241 %8 = ADDI %2, 2
2313 %3 = ADDI %2, 1
[all …]
Dexpand-isel-9.mir46 $r5 = ADDI $r3, 1
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp44 bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
91 if (LoADDI->getOpcode() != RISCV::ADDI || in detectLuiAddiGlobal()
148 if (OffsetTail.getOpcode() == RISCV::ADDI) { in matchLargeOffset()
191 case RISCV::ADDI: { in detectAndFoldOffset()
DRISCVISelDAGToDAG.cpp99 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); in Select()
183 if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI) in doPeepholeLoadStoreADDI()
DRISCVInstrInfo.td321 // ADDI isn't always rematerializable, but isReMaterializable will be used as
324 def ADDI : ALU_ri<0b000, "addi">;
462 def : InstAlias<"nop", (ADDI X0, X0, 0)>;
473 def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
579 def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
581 def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
586 def : PatGprSimm12<add, ADDI>;
604 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
606 (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
DRISCVInstrInfoC.td537 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
583 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
584 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
599 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
601 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
678 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
DRISCVInstrInfo.cpp89 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
174 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in movImm32()
/external/pcre/dist2/src/sljit/
DsljitNativePPC_64.c52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
70 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
87 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
93 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
103 FAIL_IF(push_inst(compiler, ADDI | D(reg) | A(0) | IMM(tmp >> 48))); in load_immediate()
251 return push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)); in emit_single_op()
275 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff)); in emit_single_op()
DsljitNativeARM_64.c72 #define ADDI 0x91000000 macro
608 return push_inst(compiler, ((op == SLJIT_ADD ? ADDI : SUBI) ^ inv_bits) | RD(dst) | RN(reg)); in emit_op_imm()
612 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | (imm << 10)); in emit_op_imm()
621 …return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22)… in emit_op_imm()
628 …FAIL_IF(push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(reg) | ((imm >> 12) << 10) | (1 << 22… in emit_op_imm()
629 return push_inst(compiler, (ADDI ^ inv_bits) | RD(dst) | RN(dst) | ((imm & 0xfff) << 10)); in emit_op_imm()
849 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(tmp_reg) | RN(arg) | ((argw >> 12) << 10))); in emit_op_mem()
922 FAIL_IF(push_inst(compiler, ADDI | RD(TMP_FP) | RN(SLJIT_SP) | (0 << 10))); in sljit_emit_enter()
970 FAIL_IF(push_inst(compiler, ADDI | RD(SLJIT_SP) | RN(TMP_REG1) | (0 << 10))); in sljit_emit_enter()
974 FAIL_IF(push_inst(compiler, ADDI | RD(SLJIT_SP) | RN(TMP_REG1) | (0 << 10))); in sljit_emit_enter()
[all …]
DsljitNativePPC_32.c32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
116 return push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)); in emit_single_op()
137 return push_inst(compiler, ADDI | D(dst) | A(src1) | (-compiler->imm & 0xffff)); in emit_single_op()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.cpp83 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
290 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; in eliminateCallFramePseudoInstr()
382 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
431 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
436 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
386 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
451 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
977 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1008 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp86 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
465 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
530 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
1073 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1104 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
DPPCAsmPrinter.cpp617 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDI) in EmitInstruction()
952 MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI) in EmitInstruction()
997 MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI) in EmitInstruction()
1045 MCInstBuilder(Subtarget->isPPC64() ? PPC::ADDI8 : PPC::ADDI) in EmitInstruction()
1450 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDI) in EmitFunctionBodyStart()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2InstrInfo.td98 defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dhexagon-tfr-add.ll1 …RUN: llc -march=hexagon -O2 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-ADDI
91 ; CHECK-ADDI: ##g0

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