1//===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Nios2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Instruction format superclass
16//===----------------------------------------------------------------------===//
17
18include "Nios2InstrFormats.td"
19
20
21//===----------------------------------------------------------------------===//
22// Nios2 Operand, Complex Patterns and Transformations Definitions.
23//===----------------------------------------------------------------------===//
24
25def simm16     : Operand<i32> {
26  let DecoderMethod= "DecodeSimm16";
27}
28
29// Node immediate fits as 16-bit sign extended on target immediate.
30// e.g. addi, andi
31def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
32
33// Custom return SDNode
34def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
35    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36
37//===----------------------------------------------------------------------===//
38// Instructions specific format
39//===----------------------------------------------------------------------===//
40
41// Arithmetic and logical instructions with 2 registers and 16-bit immediate
42// value.
43multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
44                              Operand immOp, PatLeaf immType>:
45           CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
46	                       (ins CPURegs:$rA, immOp:$imm),
47                               !strconcat(mnemonic, "\t$rB, $rA, $imm"),
48                               [(set CPURegs:$rB,
49			         (opNode CPURegs:$rA, immType:$imm))],
50                               IIAlu>;
51
52// Arithmetic and logical instructions with 3 register operands.
53// Defines R1 and R2 instruction at the same time.
54multiclass ArithLogicReg<bits<6> opx, string mnemonic,
55                         SDNode opNode>:
56  CommonInstr_R_F3X6<opx, (outs CPURegs:$rC),
57                     (ins CPURegs:$rA, CPURegs:$rB),
58                     !strconcat(mnemonic, "\t$rC, $rA, $rB"),
59                     [(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
60                     IIAlu>;
61
62multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
63  let rB = 0, rC = 0,
64      isReturn = 1,
65      isCodeGenOnly = 1,
66      hasCtrlDep = 1,
67      hasExtraSrcRegAllocReq = 1 in {
68    defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
69  }
70}
71
72//===----------------------------------------------------------------------===//
73// Nios2 Instructions
74//===----------------------------------------------------------------------===//
75
76/// Arithmetic instructions operating on registers.
77let isCommutable = 1 ,
78    isReMaterializable = 1 in {
79  defm ADD    : ArithLogicReg<0x31, "add",    add>;
80  defm AND    : ArithLogicReg<0x0e, "and",    and>;
81  defm OR     : ArithLogicReg<0x16, "or",     or>;
82  defm XOR    : ArithLogicReg<0x1e, "xor",    xor>;
83  defm MUL    : ArithLogicReg<0x27, "mul",    mul>;
84}
85
86let isReMaterializable = 1 in {
87  defm SUB    : ArithLogicReg<0x39, "sub",    sub>;
88}
89
90defm DIVU : ArithLogicReg<0x24, "divu",   udiv>;
91defm DIV  : ArithLogicReg<0x25, "div",    sdiv>;
92
93defm SLL : ArithLogicReg<0x13, "sll",  shl>;
94defm SRL : ArithLogicReg<0x1b, "srl",  srl>;
95defm SRA : ArithLogicReg<0x3b, "sra",  sra>;
96
97/// Arithmetic Instructions (ALU Immediate)
98defm ADDI  : ArithLogicRegImm16<0x04, "addi",  add, simm16, immSExt16>;
99
100// Returns:
101defm RET  : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
102
103//===----------------------------------------------------------------------===//
104// Pseudo instructions
105//===----------------------------------------------------------------------===//
106
107// Return RA.
108let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
109def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;
110