/external/llvm/test/CodeGen/MIR/ARM/ |
D | imm-peephole-arm.mir | 4 # CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133 5 # CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600 13 # CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133 14 # CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600
|
D | cfi-same-value.mir | 77 %sp = ADDri killed %sp, 40, 14, _, _
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | imm-peephole-arm.mir | 4 # CHECK: [[SUM1TMP:%.*]]:rgpr = ADDri [[IN]], 133 5 # CHECK: [[SUM1:%.*]]:rgpr = ADDri killed [[SUM1TMP]], 25600 13 # CHECK: [[SUM4TMP:%.*]]:rgpr = ADDri killed [[IN]], 133 14 # CHECK: [[SUM4:%.*]]:rgpr = ADDri killed [[SUM4TMP]], 25600
|
D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
|
D | fp16-litpool2-arm.mir | 105 $sp = ADDri $sp, 4, 14, $noreg, $noreg
|
D | fp16-litpool3-arm.mir | 111 $sp = ADDri $sp, 4, 14, $noreg, $noreg
|
D | fp16-litpool-arm.mir | 88 $sp = ADDri $sp, 4, 14, $noreg, $noreg
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcFrameLowering.cpp | 45 unsigned ADDri) const { in emitSPAdjustment() 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment() 120 SAVEri = SP::ADDri; in emitPrologue() 186 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased) in emitPrologue() 198 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6) in emitPrologue() 214 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); in eliminateCallFramePseudoInstr() 240 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); in emitEpilogue()
|
D | SparcFrameLowering.h | 62 int NumBytes, unsigned ADDrr, unsigned ADDri) const;
|
/external/llvm/lib/Target/Sparc/ |
D | SparcFrameLowering.cpp | 45 unsigned ADDri) const { in emitSPAdjustment() 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment() 119 SAVEri = SP::ADDri; in emitPrologue() 196 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); in eliminateCallFramePseudoInstr() 222 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); in emitEpilogue()
|
D | SparcFrameLowering.h | 62 int NumBytes, unsigned ADDrr, unsigned ADDri) const;
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86FixupLEAs.cpp | 446 const MCInstrDesc &ADDri = in processInstructionForSLM() local 449 NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR) in processInstructionForSLM() 500 const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset)); in processInstrForSlow3OpLEA() local 516 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); in processInstrForSlow3OpLEA() 536 NewMI = BuildMI(*MFI, MI, DL, ADDri, DstR).addReg(DstR).add(Offset); in processInstrForSlow3OpLEA()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | README.txt | 35 %reg1037 = ADDri %reg1039, 1 43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an 45 PHI node. We should treat it as a two-address code and make sure the ADDri is
|
/external/llvm/lib/CodeGen/ |
D | README.txt | 35 %reg1037 = ADDri %reg1039, 1 43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an 45 PHI node. We should treat it as a two-address code and make sure the ADDri is
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | README.txt | 35 %reg1037 = ADDri %reg1039, 1 43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an 45 PHI node. We should treat it as a two-address code and make sure the ADDri is
|
/external/llvm/test/CodeGen/ARM/ |
D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
|
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
|
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcRegisterInfo.cpp | 68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); in eliminateCallFramePseudoInstr()
|
D | SparcAsmPrinter.cpp | 78 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) && in printOperand()
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/ARM/ |
D | cfi-same-value.mir | 77 $sp = ADDri killed $sp, 40, 14, _, _
|
/external/llvm/lib/Target/ARM/ |
D | ARMMCInstLower.cpp | 123 case ARM::ADDri: in LowerARMMachineInstrToMCInst()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMMCInstLower.cpp | 140 case ARM::ADDri: in LowerARMMachineInstrToMCInst()
|
D | ARMBaseInstrInfo.cpp | 192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 223 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 2165 {ARM::ADDSri, ARM::ADDri}, 2238 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate() 2380 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex() 2628 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) && in isRedundantFlagInstr() 2657 case ARM::ADDri: in isOptimizeCompareCandidate() 3031 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate() 3034 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress() 1470 {ARM::ADDSri, ARM::ADDri}, 1528 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate() 1549 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex() 1801 case ARM::ADDri: in OptimizeCompareInstr() 1926 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; in FoldImmediate()
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/ARM/ |
D | live-debug-values-reg-copy.mir | 134 renamable $r4 = ADDri killed renamable $r0, 10, 14, $noreg, $noreg, debug-location !16
|