| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType()
66 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
491 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
495 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
501 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
507 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
512 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, in shouldReduceLoadWidth()
535 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, in isLoadBitCastBeneficial()
554 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const { in isCheapToSpeculateCttz()
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| D | AMDGPUTargetTransformInfo.h | 26 class AMDGPUTargetLowering; variable
34 const AMDGPUTargetLowering *TLI;
37 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
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| D | AMDGPUCallLowering.h | 22 class AMDGPUTargetLowering; variable
26 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
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| D | AMDGPUCallLowering.cpp | 28 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) in AMDGPUCallLowering()
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| D | AMDGPUSubtarget.h | 121 const AMDGPUTargetLowering *getTargetLowering() const override;
446 inline const AMDGPUTargetLowering *AMDGPUSubtarget::getTargetLowering() const { in getTargetLowering()
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| D | AMDGPUISelLowering.h | 27 class AMDGPUTargetLowering : public TargetLowering {
121 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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| D | R600ISelLowering.h | 25 class R600TargetLowering final : public AMDGPUTargetLowering {
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| D | R600ISelLowering.cpp | 35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) { in R600TargetLowering()
238 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
671 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
833 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
921 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1355 if (SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG)) in LowerSTORE()
1953 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
2070 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2166 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
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| D | SIISelLowering.h | 23 class SITargetLowering final : public AMDGPUTargetLowering {
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| D | SIISelLowering.cpp | 57 : AMDGPUTargetLowering(TM, STI) { in SITargetLowering()
947 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, in LowerReturn()
1159 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
1230 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
1567 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1915 return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
2522 if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI)) in performAndCombine()
2865 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3061 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3378 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); in CreateLiveInRegister()
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| D | AMDGPUISelDAGToDAG.cpp | 1551 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG()
1552 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); in PostprocessISelDAG()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 121 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
130 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned()
138 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned()
146 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
606 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N, in allUsesHaveSourceMods()
630 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
634 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
640 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
647 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
652 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, in shouldReduceLoadWidth()
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| D | AMDGPUTargetTransformInfo.h | 36 class AMDGPUTargetLowering; variable
66 const AMDGPUTargetLowering *TLI;
95 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
210 const AMDGPUTargetLowering *TLI;
221 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
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| D | AMDGPUCallLowering.h | 23 class AMDGPUTargetLowering; variable
36 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
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| D | AMDGPUCallLowering.cpp | 30 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) in AMDGPUCallLowering()
180 const AMDGPUTargetLowering &TLI = *getTLI<AMDGPUTargetLowering>(); in lowerFormalArguments()
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| D | R600ISelLowering.h | 25 class R600TargetLowering final : public AMDGPUTargetLowering {
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| D | AMDGPUISelLowering.h | 29 class AMDGPUTargetLowering : public TargetLowering {
131 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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| D | R600ISelLowering.cpp | 57 : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) { in R600TargetLowering()
317 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
477 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
655 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
745 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1963 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2068 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
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| D | SIISelLowering.h | 24 class SITargetLowering final : public AMDGPUTargetLowering {
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| D | AMDGPUISelDAGToDAG.cpp | 2121 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG()
2122 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); in PostprocessISelDAG()
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| D | SIISelLowering.cpp | 116 : AMDGPUTargetLowering(TM, STI), in SITargetLowering()
2034 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, in LowerReturn()
3468 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
3591 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
4419 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
6797 return AMDGPUTargetLowering::performRcpCombine(N, DCI); in performRcpCombine()
7796 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
7917 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
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