1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "AMDGPUArgumentUsageInfo.h" 20 #include "SIInstrInfo.h" 21 22 namespace llvm { 23 24 class SITargetLowering final : public AMDGPUTargetLowering { 25 private: 26 const GCNSubtarget *Subtarget; 27 28 public: 29 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 30 CallingConv::ID CC, 31 EVT VT) const override; 32 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 33 CallingConv::ID CC, 34 EVT VT) const override; 35 36 unsigned getVectorTypeBreakdownForCallingConv( 37 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 38 unsigned &NumIntermediates, MVT &RegisterVT) const override; 39 40 private: 41 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 42 SDValue Chain, uint64_t Offset) const; 43 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 44 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 45 const SDLoc &SL, SDValue Chain, 46 uint64_t Offset, unsigned Align, bool Signed, 47 const ISD::InputArg *Arg = nullptr) const; 48 49 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 50 const SDLoc &SL, SDValue Chain, 51 const ISD::InputArg &Arg) const; 52 SDValue getPreloadedValue(SelectionDAG &DAG, 53 const SIMachineFunctionInfo &MFI, 54 EVT VT, 55 AMDGPUFunctionArgInfo::PreloadedValue) const; 56 57 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 58 SelectionDAG &DAG) const override; 59 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 60 MVT VT, unsigned Offset) const; 61 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 62 SelectionDAG &DAG) const; 63 64 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 65 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 66 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 67 68 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 69 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 70 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 71 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 72 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 73 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 74 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 75 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 76 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 77 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 78 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 79 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 81 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 82 83 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 84 SelectionDAG &DAG, 85 bool IsIntrinsic = false) const; 86 87 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const; 88 89 /// Converts \p Op, which must be of floating point type, to the 90 /// floating point type \p VT, by either extending or truncating it. 91 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG, 92 SDValue Op, 93 const SDLoc &DL, 94 EVT VT) const; 95 96 SDValue convertArgType( 97 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 98 bool Signed, const ISD::InputArg *Arg = nullptr) const; 99 100 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 101 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 102 103 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 104 SelectionDAG &DAG) const; 105 106 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 107 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 108 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 109 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 110 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 111 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 112 113 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 114 115 SDValue performUCharToFloatCombine(SDNode *N, 116 DAGCombinerInfo &DCI) const; 117 SDValue performSHLPtrCombine(SDNode *N, 118 unsigned AS, 119 EVT MemVT, 120 DAGCombinerInfo &DCI) const; 121 122 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 123 124 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 125 unsigned Opc, SDValue LHS, 126 const ConstantSDNode *CRHS) const; 127 128 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 129 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 130 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 131 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 132 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 133 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 134 135 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 136 SDValue Op0, SDValue Op1) const; 137 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 138 SDValue Op0, SDValue Op1, bool Signed) const; 139 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 140 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 141 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 142 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 143 SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 144 145 unsigned getFusedOpcode(const SelectionDAG &DAG, 146 const SDNode *N0, const SDNode *N1) const; 147 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 148 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 149 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 150 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 151 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 152 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 153 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 154 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 155 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 156 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 157 158 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 159 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 160 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 161 162 unsigned isCFIntrinsic(const SDNode *Intr) const; 163 164 void createDebuggerPrologueStackObjects(MachineFunction &MF) const; 165 166 /// \returns True if fixup needs to be emitted for given global value \p GV, 167 /// false otherwise. 168 bool shouldEmitFixup(const GlobalValue *GV) const; 169 170 /// \returns True if GOT relocation needs to be emitted for given global value 171 /// \p GV, false otherwise. 172 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 173 174 /// \returns True if PC-relative relocation needs to be emitted for given 175 /// global value \p GV, false otherwise. 176 bool shouldEmitPCReloc(const GlobalValue *GV) const; 177 178 public: 179 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 180 181 const GCNSubtarget *getSubtarget() const; 182 183 bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override; 184 185 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 186 187 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 188 MachineFunction &MF, 189 unsigned IntrinsicID) const override; 190 191 bool getAddrModeArguments(IntrinsicInst * /*I*/, 192 SmallVectorImpl<Value*> &/*Ops*/, 193 Type *&/*AccessTy*/) const override; 194 195 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 196 unsigned AS, 197 Instruction *I = nullptr) const override; 198 199 bool canMergeStoresTo(unsigned AS, EVT MemVT, 200 const SelectionDAG &DAG) const override; 201 202 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 203 unsigned Align, 204 bool *IsFast) const override; 205 206 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 207 unsigned SrcAlign, bool IsMemset, 208 bool ZeroMemset, 209 bool MemcpyStrSrc, 210 MachineFunction &MF) const override; 211 212 bool isMemOpUniform(const SDNode *N) const; 213 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 214 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 215 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 216 217 TargetLoweringBase::LegalizeTypeAction 218 getPreferredVectorAction(EVT VT) const override; 219 220 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 221 Type *Ty) const override; 222 223 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 224 225 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 226 227 bool supportSplitCSR(MachineFunction *MF) const override; 228 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 229 void insertCopiesSplitCSR( 230 MachineBasicBlock *Entry, 231 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 232 233 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 234 bool isVarArg, 235 const SmallVectorImpl<ISD::InputArg> &Ins, 236 const SDLoc &DL, SelectionDAG &DAG, 237 SmallVectorImpl<SDValue> &InVals) const override; 238 239 bool CanLowerReturn(CallingConv::ID CallConv, 240 MachineFunction &MF, bool isVarArg, 241 const SmallVectorImpl<ISD::OutputArg> &Outs, 242 LLVMContext &Context) const override; 243 244 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 245 const SmallVectorImpl<ISD::OutputArg> &Outs, 246 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 247 SelectionDAG &DAG) const override; 248 249 void passSpecialInputs( 250 CallLoweringInfo &CLI, 251 const SIMachineFunctionInfo &Info, 252 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 253 SmallVectorImpl<SDValue> &MemOpChains, 254 SDValue Chain, 255 SDValue StackPtr) const; 256 257 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 258 CallingConv::ID CallConv, bool isVarArg, 259 const SmallVectorImpl<ISD::InputArg> &Ins, 260 const SDLoc &DL, SelectionDAG &DAG, 261 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 262 SDValue ThisVal) const; 263 264 bool mayBeEmittedAsTailCall(const CallInst *) const override; 265 266 bool isEligibleForTailCallOptimization( 267 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 268 const SmallVectorImpl<ISD::OutputArg> &Outs, 269 const SmallVectorImpl<SDValue> &OutVals, 270 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 271 272 SDValue LowerCall(CallLoweringInfo &CLI, 273 SmallVectorImpl<SDValue> &InVals) const override; 274 275 unsigned getRegisterByName(const char* RegName, EVT VT, 276 SelectionDAG &DAG) const override; 277 278 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 279 MachineBasicBlock *BB) const; 280 281 MachineBasicBlock * 282 EmitInstrWithCustomInserter(MachineInstr &MI, 283 MachineBasicBlock *BB) const override; 284 285 bool hasBitPreservingFPLogic(EVT VT) const override; 286 bool enableAggressiveFMAFusion(EVT VT) const override; 287 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 288 EVT VT) const override; 289 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 290 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 291 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 292 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 293 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 294 295 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 296 SelectionDAG &DAG) const override; 297 298 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 299 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 300 void AdjustInstrPostInstrSelection(MachineInstr &MI, 301 SDNode *Node) const override; 302 303 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 304 305 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 306 SDValue Ptr) const; 307 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 308 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 309 std::pair<unsigned, const TargetRegisterClass *> 310 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 311 StringRef Constraint, MVT VT) const override; 312 ConstraintType getConstraintType(StringRef Constraint) const override; 313 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 314 SDValue V) const; 315 316 void finalizeLowering(MachineFunction &MF) const override; 317 318 void computeKnownBitsForFrameIndex(const SDValue Op, 319 KnownBits &Known, 320 const APInt &DemandedElts, 321 const SelectionDAG &DAG, 322 unsigned Depth = 0) const override; 323 324 bool isSDNodeSourceOfDivergence(const SDNode *N, 325 FunctionLoweringInfo *FLI, DivergenceAnalysis *DA) const override; 326 }; 327 328 } // End namespace llvm 329 330 #endif 331