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Searched refs:APCS (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dlarge-vector.ll3 …lc -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-APCS
18 ; CHECK-APCS: add r[[BASE:[0-9]+]], sp, #76
19 ; CHECK-APCS: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
20 ; CHECK-APCS: add r[[BASE:[0-9]+]], sp, #60
21 ; CHECK-APCS: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
39 ; CHECK-APCS: add r[[BASE:[0-9]+]], sp, #60
40 ; CHECK-APCS: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
41 ; CHECK-APCS: mov r[[BASE:[0-9]+]], sp
42 ; CHECK-APCS: str {{r[0-9]+}}, [r[[BASE]]], #76
43 ; CHECK-APCS: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
Darm-abi-attr.ll3 ; RUN: FileCheck %s --check-prefix=APCS
5 ; RUN: FileCheck %s --check-prefix=APCS
13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
14 ; only on APCS.
17 ; APCS: sub sp, sp, #8
18 ; APCS: bic sp, sp, #7
Dbyval-align.ll3 ; This checks that alignments greater than 4 are respected by APCS
5 ; simplifying refactoring; at the time of writing there were no actual APCS
Dtail-call.ll64 ; that %z is passed in r1-r2 if APCS is used, contrary to AAPCS where r2-r3
/external/llvm/test/CodeGen/ARM/
Darm-abi-attr.ll1 ; RUN: llc -mtriple=arm-linux-gnu < %s | FileCheck %s --check-prefix=APCS
3 ; RUN: FileCheck %s --check-prefix=APCS
5 ; RUN: FileCheck %s --check-prefix=APCS
13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
14 ; only on APCS.
17 ; APCS: sub sp, sp, #8
18 ; APCS: bic sp, sp, #7
Dbyval-align.ll3 ; This checks that alignments greater than 4 are respected by APCS
5 ; simplifying refactoring; at the time of writing there were no actual APCS
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCallingConv.td21 // ARM APCS Calling Convention
59 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
86 // ARM APCS Calling Convention for GHC
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMCallingConv.td17 // ARM APCS Calling Convention
68 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
102 // ARM APCS Calling Convention for GHC
/external/llvm/lib/Target/ARM/
DARMCallingConv.td17 // ARM APCS Calling Convention
68 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
102 // ARM APCS Calling Convention for GHC
/external/python/cpython2/RISCOS/
DMakefile29 CFLAGS = -c $(DLKFLAG) -DRISCOS -DHAVE_CONFIG_H -wadP -throwback -APCS 3/32bit/fpe3
389 ObjAsm -APCS 3/32bit s.linktab o.linktab
/external/clang/lib/CodeGen/
DTargetInfo.cpp4985 APCS = 0, enumerator
5109 if (ABI == ARMABIInfo::APCS) in setTargetAttributes()
5182 case APCS: return llvm::CallingConv::ARM_APCS; in getABIDefaultCC()
5203 case APCS: in setCCs()
5467 if (getABIKind() == APCS) { in classifyReturnType()
7994 Kind = ARMABIInfo::APCS; in getTargetCodeGenInfo()
/external/libffi/
DChangeLog.libffi-3.14117 * src/arm/sysv.S (ffi_call_SYSV): Rework to avoid use of APCS register
/external/python/cpython2/Modules/_ctypes/libffi/
DChangeLog.libffi-3.14117 * src/arm/sysv.S (ffi_call_SYSV): Rework to avoid use of APCS register