Searched refs:AR71XX_DDR_REG_CONTROL (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/arch/mips/mach-ath79/ar933x/ |
| D | ddr.c | 123 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
129 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
134 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
140 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
146 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
149 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
152 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
153 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
158 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
164 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
[all …]
|
| /external/u-boot/arch/mips/mach-ath79/qca953x/ |
| D | ddr.c | 254 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
262 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
270 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
274 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
278 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
280 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
288 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
301 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
303 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
336 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
[all …]
|
| /external/u-boot/arch/mips/mach-ath79/ar934x/ |
| D | ddr.c | 69 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
72 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
98 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
104 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
111 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
120 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
123 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
129 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); in ar934x_ddr_init()
|
| /external/u-boot/arch/mips/mach-ath79/include/mach/ |
| D | ar71xx_regs.h | 211 #define AR71XX_DDR_REG_CONTROL 0x10 macro
|