1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
4 *
5 * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/addrspace.h>
11 #include <asm/types.h>
12 #include <mach/ar71xx_regs.h>
13 #include <mach/ath79.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 enum {
18 AR934X_SDRAM = 0,
19 AR934X_DDR1,
20 AR934X_DDR2,
21 };
22
23 struct ar934x_mem_config {
24 u32 config1;
25 u32 config2;
26 u32 mode;
27 u32 extmode;
28 u32 tap;
29 };
30
31 static const struct ar934x_mem_config ar934x_mem_config[] = {
32 [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
33 [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
34 [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
35 };
36
ar934x_ddr_init(const u16 cpu_mhz,const u16 ddr_mhz,const u16 ahb_mhz)37 void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
38 {
39 void __iomem *ddr_regs;
40 const struct ar934x_mem_config *memcfg;
41 int memtype;
42 u32 reg, cycle, ctl;
43
44 ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
45 MAP_NOCACHE);
46
47 reg = ath79_get_bootstrap();
48 if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
49 if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
50 memtype = AR934X_DDR1;
51 cycle = 0xffff;
52 } else { /* DDR 2 */
53 memtype = AR934X_DDR2;
54 if (gd->arch.rev) {
55 ctl = BIT(6); /* Undocumented bit :-( */
56 if (reg & BIT(3))
57 cycle = 0xff;
58 else
59 cycle = 0xffff;
60 } else {
61 /* Force DDR2/x16 configuratio on old chips. */
62 ctl = 0;
63 cycle = 0xffff; /* DDR2 16bit */
64 }
65
66 writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
67 udelay(100);
68
69 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
70 udelay(10);
71
72 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
73 udelay(10);
74
75 writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
76 udelay(10);
77 }
78 } else { /* SDRAM */
79 memtype = AR934X_SDRAM;
80 cycle = 0xffffffff;
81
82 writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
83 udelay(100);
84
85 /* Undocumented register */
86 writel(0x13b, ddr_regs + 0x118);
87 udelay(100);
88 }
89
90 memcfg = &ar934x_mem_config[memtype];
91
92 writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
93 udelay(100);
94
95 writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
96 udelay(100);
97
98 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
99 udelay(10);
100
101 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
102 mdelay(1);
103
104 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
105 udelay(10);
106
107 if (memtype == AR934X_DDR2) {
108 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
109 udelay(100);
110
111 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
112 udelay(10);
113 }
114
115 if (memtype != AR934X_SDRAM)
116 writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
117
118 udelay(100);
119
120 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
121 udelay(10);
122
123 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
124 udelay(10);
125
126 writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
127 udelay(100);
128
129 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
130 udelay(10);
131
132 writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
133 udelay(100);
134
135 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
136 writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
137
138 if (memtype != AR934X_SDRAM) {
139 if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
140 writel(memcfg->tap,
141 ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
142 writel(memcfg->tap,
143 ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
144 }
145 }
146
147 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
148 udelay(100);
149
150 writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
151 udelay(100);
152
153 writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
154 udelay(100);
155
156 writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
157 udelay(100);
158 }
159
ddr_tap_tuning(void)160 void ddr_tap_tuning(void)
161 {
162 }
163