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Searched refs:Amt2 (Results 1 – 15 of 15) sorted by relevance

/external/llvm/test/CodeGen/X86/
Drotate.ll7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
8 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
18 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
42 %shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
51 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
52 %shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
74 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
75 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Drotate.ll7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
8 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
18 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
42 %shift.upgrd.6 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
51 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
52 %shift.upgrd.8 = zext i8 %Amt2 to i16 ; <i16> [#uses=1]
74 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
75 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Drotl-2.ll8 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
9 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
18 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
19 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
Drotl-64.ll15 %Amt2 = sub i8 64, %Amt
16 %Amt3 = zext i8 %Amt2 to i64
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Drotl-2.ll9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
10 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
20 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
Drotl-64.ll15 %Amt2 = sub i8 64, %Amt
16 %Amt3 = zext i8 %Amt2 to i64
/external/llvm/test/CodeGen/PowerPC/
Drotl-2.ll9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
10 %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
20 %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
Drotl-64.ll15 %Amt2 = sub i8 64, %Amt
16 %Amt3 = zext i8 %Amt2 to i64
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Drotate_ops.ll67 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
68 %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
75 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
78 %tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
135 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
136 %C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
143 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
144 %C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Drotate.ll51 %Amt2 = sub i8 64, %Amt
52 %shift.upgrd.2 = zext i8 %Amt2 to i64
104 %Amt2 = sub i8 64, %Amt
105 %shift.upgrd.4 = zext i8 %Amt2 to i64
211 %Amt2 = sub i8 32, %Amt
212 %shift.upgrd.2 = zext i8 %Amt2 to i32
234 %Amt2 = sub i8 32, %Amt
235 %shift.upgrd.4 = zext i8 %Amt2 to i32
329 %Amt2 = sub i8 16, %Amt
330 %shift.upgrd.6 = zext i8 %Amt2 to i16
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1399 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, in ExpandShiftWithKnownAmountBit()
1413 DAG.getNode(Op2, NVT, InL, Amt2)); in ExpandShiftWithKnownAmountBit()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1640 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, in ExpandShiftWithKnownAmountBit() local
1659 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); in ExpandShiftWithKnownAmountBit()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1565 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, in ExpandShiftWithKnownAmountBit() local
1584 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); in ExpandShiftWithKnownAmountBit()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp23468 SDValue Amt1, Amt2; in LowerShift() local
23482 if (!Amt2 || Amt2 == A) { in LowerShift()
23484 Amt2 = A; in LowerShift()
23491 if (ShuffleMask.size() == NumElts && Amt1 && Amt2 && in LowerShift()
23492 isa<ConstantSDNode>(Amt1) && isa<ConstantSDNode>(Amt2) && in LowerShift()
23501 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT); in LowerShift()
23538 SDValue Amt0, Amt1, Amt2, Amt3; in LowerShift() local
23542 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2}); in LowerShift()
23567 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1}); in LowerShift()
23577 Amt2 = DAG.getVectorShuffle(MVT::v8i16, dl, Amt23, Amt23, in LowerShift()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp9896 SDValue Amt1, Amt2; in LowerShift() local
9908 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, in LowerShift()
9913 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), in LowerShift()
9919 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); in LowerShift()