| /external/clang/test/Layout/ |
| D | ms-x86-lazy-empty-nonvirtual-base.cpp | 18 struct B10 { char c[7]; B10() { printf("B10 = %p\n", this); } }; in B10() struct
239 struct AA2 : B10, B1, virtual B0 {
267 struct AB2 : B10, B1, virtual B0 {
293 struct AC2 : B10, B1, virtual B0 {
319 struct AD2 : B10, B1, virtual B0 {
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| /external/cldr/tools/java/org/unicode/cldr/draft/keyboard/osx/ |
| D | osx-keycodes.csv | 50 44,B10
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| /external/cldr/tools/java/org/unicode/cldr/draft/keyboard/windows/ |
| D | windows-keycodes.csv | 49 53,B10
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| /external/cldr/tools/java/org/unicode/cldr/draft/keyboard/ |
| D | IsoLayoutPosition.java | 46 …"."), B10('B', 10, "/"), B11('B', 11, "(key to right of /)"), B12('B', 12, "(2 keys to right of /)… enumConstant
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 570 B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
586 B11 | B10 | B9 | B8 | B7 | B4 |
1267 EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
1278 EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm); in vsubqs()
1290 EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
1296 EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
1303 EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
1328 EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
1334 EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm); in vminqs()
1339 EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm); in vmaxqs()
[all …]
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| D | assembler_arm.h | 56 B10 = 1 << 10,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 226 def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>;
260 def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
295 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
330 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
365 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 46 static constexpr IValueT B10 = 1 << 10; variable
1205 (getXXXXInRegYXXXX(Dd) << 12) | (IsFloatTy ? B10 : 0) | in emitSIMDBase()
1258 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode; in emitSIMDCvtqq()
1650 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp()
2142 B17 | B16 | B11 | B10 | B9 | B8 | B5 | B4; in rbit()
2154 B16 | B11 | B10 | B9 | B8 | B5 | B4; in rev()
2463 constexpr IValueT VceqOpcode = B11 | B10 | B9; in vceqqs()
2499 constexpr IValueT VcgeOpcode = B24 | B11 | B10 | B9; in vcgeqs()
2535 constexpr IValueT VcgeOpcode = B24 | B21 | B11 | B10 | B9; in vcgtqs()
3355 B25 | (Unsigned ? B24 : 0) | B23 | (B20) | B11 | B10; in vmulh()
[all …]
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 122 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
162 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 122 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
162 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 245 def B10 : AArch64Reg<10, "b10">, DwarfRegNum<[74]>;
279 def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
314 def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
349 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
384 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | fmaddsub-combine.ll | 297 %B10 = extractelement <16 x float> %B, i32 10
298 %sub10 = fsub float %A10, %B10
566 %B10 = extractelement <16 x float> %B, i32 10
567 %sub10 = fadd float %A10, %B10
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| D | combine-srem.ll | 427 %B10 = udiv i32 %L6, %B14
428 %B6 = and i32 %B16, %B10
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 173 B10 = 1 << 10, enumerator
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| D | assembler-arm.cc | 4109 op_encoding = B10 | 0x3 * B7; in EncodeNeonUnaryOp()
4120 op_encoding = B16 | B10 | 0x6 * B7; in EncodeNeonUnaryOp()
4127 op_encoding = B16 | B10 | 0x7 * B7; in EncodeNeonUnaryOp()
4910 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 | 0x2 * B10 | in EncodeNeonVTB()
|
| /external/harfbuzz_ng/test/shaping/data/in-house/tests/ |
| D | indic-vowel-letter-spoofing.tests | 39 ../fonts/2c25beb56d9c556622d56b0b5d02b4670c034f89.ttf::U+0B10,U+0020,U+0B0F,U+0B57:[aiorya=0+1681|s…
|
| /external/cldr/tools/java/org/unicode/cldr/draft/ |
| D | Keyboard.java | 45 …C09, C10, C11, C12, C13, B00, B01, B02, B03, B04, B05, B06, B07, B08, B09, B10, B11, B12, B13, A00… enumConstant
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| /external/pcre/dist2/ |
| D | RunGrepTest | 229 (cd $srcdir; $valgrind $vjs $pcre2grep -C12 -B10 'four' ./testdata/grepinputx) >>testtrygrep
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| D | RunGrepTest.bat | 207 (pushd %srcdir% & %pcre2grep% -C12 -B10 "four" ./testdata/grepinputx & popd) >>testtrygrep
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | shift-lshr.ll | 153 ; SSE-NEXT: [[B10:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i…
169 ; SSE-NEXT: [[R10:%.*]] = lshr i32 [[A10]], [[B10]]
333 ; SSE-NEXT: [[B10:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i…
365 ; SSE-NEXT: [[R10:%.*]] = lshr i16 [[A10]], [[B10]]
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| D | shift-ashr.ll | 185 ; SSE-NEXT: [[B10:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i…
201 ; SSE-NEXT: [[R10:%.*]] = ashr i32 [[A10]], [[B10]]
384 ; SSE-NEXT: [[B10:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i…
416 ; SSE-NEXT: [[R10:%.*]] = ashr i16 [[A10]], [[B10]]
|
| D | fma.ll | 402 ; NO-FMA-NEXT: [[B10:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x floa…
434 ; NO-FMA-NEXT: [[FMA10:%.*]] = call float @llvm.fma.f32(float [[A10]], float [[B10]], float [[C1…
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | shift.ll | 1509 %B10 = sub i177 %B5, %B3
1514 %B1 = udiv i177 %B10, %B6
|
| /external/deqp/framework/common/ |
| D | tcuAstcUtil.cpp | 1999 #define ASSIGN_BITS(B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0) do { SB(10,(B10)); SB(9,(B9)); SB(… in writeBlockMode() argument
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | fma.ll | 402 ; NO-FMA-NEXT: [[B10:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x floa…
434 ; NO-FMA-NEXT: [[FMA10:%.*]] = call float @llvm.fma.f32(float [[A10]], float [[B10]], float [[C1…
|