| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 267 BFM, // Insert a range of bits into a 32-bit word. enumerator
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| D | AMDGPUInstrInfo.td | 202 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 3478 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
3481 (BFM $a, $b)
3486 (BFM $a, (MOV 0))
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| D | AMDGPUISelLowering.cpp | 2838 NODE_NAME_CASE(BFM) in getTargetNodeName()
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_fmt_def.inc | 483 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
494 BC_FIELD(TEX_WORD0, BC_FRAC_MODE, BFM, 5, 5)
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 396 BFM, // Insert a range of bits into a 32-bit word. enumerator
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| D | AMDGPUInstrInfo.td | 304 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 1570 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
1573 (BFM $a, $b)
1578 (BFM $a, (MOV (i32 0)))
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| D | SIISelLowering.cpp | 4262 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
4266 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
4268 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert.ll | 200 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert.ll | 200 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 169 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedA57.td | 159 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
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| D | AArch64ISelDAGToDAG.cpp | 1734 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1737 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
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| D | AArch64SchedKryoDetails.td | 448 (instregex "(S|U)?BFM.*")>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 171 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedThunderX2T99.td | 554 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "^BFM")>;
555 def : InstRW<[THX2T99Write_1Cyc_I012], (instregex "(S|U)?BFM.*")>;
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| D | AArch64SchedA57.td | 161 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
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| D | AArch64ISelDAGToDAG.cpp | 1804 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in tryBitfieldExtractOp() local
1807 MVT::i32, SDValue(BFM, 0), SubReg)); in tryBitfieldExtractOp()
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| D | AArch64SchedFalkorDetails.td | 1206 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(S|U)?BFM(W|X)ri$")>;
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| D | AArch64SchedKryoDetails.td | 448 (instregex "(S|U)?BFM.*")>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 662 BFM = BFM_w, enumerator
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| D | assembler-arm64.cc | 1307 Emit(SF(rd) | BFM | N | in bfm()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 627 BFM = BFM_w, enumerator
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 134 ### BFM ### subsection
|