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Searched refs:BaseOpc (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/TableGen/
Dpr8330.td14 multiclass X<bits<8> BaseOpc> {
15 def bar : Whatev<Or4<BaseOpc>.V >;
18 multiclass Y<bits<8> BaseOpc> {
19 def foo : Whatever<Or4<BaseOpc>.V >;
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
Dpr8330.td14 multiclass X<bits<8> BaseOpc> {
15 def bar : Whatev<Or4<BaseOpc>.V >;
18 multiclass Y<bits<8> BaseOpc> {
19 def foo : Whatever<Or4<BaseOpc>.V >;
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td883 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
891 def #NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
892 def #NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
893 def #NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
894 def #NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
921 def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
922 def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
923 def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
924 def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
954 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td909 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
916 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
918 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
919 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
920 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
950 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
951 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
952 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
953 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
996 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
[all …]
DX86FastISel.cpp2907 unsigned BaseOpc, CondOpc; in fastLowerIntrinsicCall() local
2911 BaseOpc = UseIncDec ? unsigned(X86ISD::INC) : unsigned(ISD::ADD); in fastLowerIntrinsicCall()
2915 BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2917 BaseOpc = UseIncDec ? unsigned(X86ISD::DEC) : unsigned(ISD::SUB); in fastLowerIntrinsicCall()
2921 BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2923 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2925 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2941 if (BaseOpc == X86ISD::INC || BaseOpc == X86ISD::DEC) { in fastLowerIntrinsicCall()
2943 bool IsDec = BaseOpc == X86ISD::DEC; in fastLowerIntrinsicCall()
2948 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td952 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
959 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
961 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
962 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
963 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
992 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
993 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
994 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
995 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
1035 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
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DX86FastISel.cpp2724 unsigned BaseOpc, CondOpc; in fastLowerIntrinsicCall() local
2728 BaseOpc = UseIncDec ? unsigned(X86ISD::INC) : unsigned(ISD::ADD); in fastLowerIntrinsicCall()
2732 BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2734 BaseOpc = UseIncDec ? unsigned(X86ISD::DEC) : unsigned(ISD::SUB); in fastLowerIntrinsicCall()
2738 BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2740 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2742 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2758 if (BaseOpc == X86ISD::INC || BaseOpc == X86ISD::DEC) { in fastLowerIntrinsicCall()
2760 bool IsDec = BaseOpc == X86ISD::DEC; in fastLowerIntrinsicCall()
2765 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp697 int BaseOpc = in CreateLoadStoreMulti() local
705 BaseOpc = in CreateLoadStoreMulti()
727 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
745 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
747 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
752 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
758 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp669 int BaseOpc = in CreateLoadStoreMulti() local
677 BaseOpc = in CreateLoadStoreMulti()
699 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
717 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
719 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
724 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase), true) in CreateLoadStoreMulti()
728 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp333 int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri; in MergeOps() local
335 BaseOpc = !isThumb2 ? ARM::SUBri : ARM::t2SUBri; in MergeOps()
344 BuildMI(MBB, MBBI, dl, TII->get(BaseOpc), NewBase) in MergeOps()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2694 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
2695 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
2703 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()