| /external/u-boot/arch/sh/cpu/sh4/ |
| D | cache.c | 42 ccr = inl(CCR); in cache_control()
48 outl(CCR_CACHE_STOP, CCR); in cache_control()
50 outl(CCR_CACHE_INIT, CCR); in cache_control()
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| /external/u-boot/doc/ |
| D | README.ne2000 | 3 that the CCR is correctly initialized.
26 - Address of the CCR (card configuration register). It could be found
32 - The value to be written in the CCR. It selects among different I/O
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| /external/u-boot/arch/sh/include/asm/ |
| D | cpu_sh7763.h | 11 #define CCR 0xFF00001C macro
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| D | cpu_sh7269.h | 6 #define CCR CCR1 macro
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| D | cpu_sh7264.h | 6 #define CCR CCR1 macro
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| D | cpu_sh7203.h | 6 #define CCR CCR1 macro
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| D | cpu_sh7706.h | 9 #define CCR 0xFFFFFFEC macro
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| D | cpu_sh7710.h | 9 #define CCR 0xFFFFFFEC macro
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| D | cpu_sh7734.h | 11 #define CCR 0xFF00001C macro
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| D | cpu_sh7750.h | 28 #define CCR 0xFF00001C macro
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| D | cpu_sh7785.h | 20 #define CCR 0xFF00001C macro
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| D | cpu_sh7723.h | 29 #define CCR 0xFF00001C macro
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| D | cpu_sh7724.h | 29 #define CCR 0xFF00001C macro
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| D | cpu_sh7757.h | 9 #define CCR 0xFF00001C macro
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| D | cpu_sh7752.h | 9 #define CCR 0xFF00001C macro
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| D | cpu_sh7753.h | 9 #define CCR 0xFF00001C macro
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| D | cpu_sh7720.h | 30 #define CCR 0xFFFFFFEC macro
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 248 ARMCC::CondCodes CCVal, SDValue CCR,
251 ARMCC::CondCodes CCVal, SDValue CCR,
254 ARMCC::CondCodes CCVal, SDValue CCR,
257 ARMCC::CondCodes CCVal, SDValue CCR,
2105 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVShiftOp() argument
2124 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag }; in SelectT2CMOVShiftOp()
2132 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectARMCMOVShiftOp() argument
2138 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag }; in SelectARMCMOVShiftOp()
2144 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag }; in SelectARMCMOVShiftOp()
2152 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { in SelectT2CMOVImmOp() argument
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBanks.td | 20 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| /external/u-boot/board/renesas/r2dplus/ |
| D | lowlevel_init.S | 73 CCR_A: .long CCR /* Cache Control Register */
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| /external/u-boot/board/ms7750se/ |
| D | lowlevel_init.S | 100 CCR_A: .long CCR
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 172 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
175 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
332 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 61 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 61 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
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| /external/u-boot/board/ms7722se/ |
| D | lowlevel_init.S | 133 CCR_A: .long CCR
|