| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCBaseInfo.h | 37 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; in getPPCRegisterNumbering()
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| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …IZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR…
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 48 Reg = PPC::CR6; in getCRFromCRBit()
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| D | PPCInstrAltivec.td | 780 let Defs = [CR6];
1228 let Defs = [CR6];
1344 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
1349 let Defs = [CR6];
1357 let Defs = [CR6];
1370 let Defs = [CR6] in
1375 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
1380 let Defs = [CR6];
1387 let Defs = [CR6];
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| D | PPCRegisterInfo.td | 200 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
344 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
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| D | PPCInstr64Bit.td | 979 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
988 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1011 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1020 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.h | 48 Reg = PPC::CR6; in getCRFromCRBit()
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| D | PPCInstrAltivec.td | 787 let Defs = [CR6];
1440 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
1445 let Defs = [CR6];
1453 let Defs = [CR6];
1466 let Defs = [CR6] in
1471 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
1476 let Defs = [CR6];
1483 let Defs = [CR6];
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| D | PPCRegisterInfo.td | 208 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
369 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
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| D | PPCInstr64Bit.td | 1117 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1126 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1149 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1158 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 185 case PPC::CR6: RegNo = 6; break; in printcrbitm()
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| /external/clang/lib/CodeGen/ |
| D | CGExprScalar.cpp | 2846 enum { CR6_EQ=0, CR6_EQ_REV, CR6_LT, CR6_LT_REV } CR6; in EmitCompare() local
2861 CR6 = CR6_LT; in EmitCompare()
2865 CR6 = CR6_EQ; in EmitCompare()
2869 CR6 = CR6_LT; in EmitCompare()
2874 CR6 = CR6_LT; in EmitCompare()
2879 CR6 = CR6_LT; in EmitCompare()
2884 CR6 = CR6_EQ; in EmitCompare()
2890 CR6 = CR6_LT; in EmitCompare()
2894 CR6 = CR6_EQ; in EmitCompare()
2901 Value *CR6Param = Builder.getInt32(CR6); in EmitCompare()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 443 Reg = PPC::CR6; in StoreRegToStackSlot()
572 Reg = PPC::CR6; in LoadRegFromStackSlot()
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| D | PPCRegisterInfo.td | 245 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
316 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
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| D | PPCInstr64Bit.td | 73 CR0,CR1,CR5,CR6,CR7,CARRY] in {
99 CR0,CR1,CR5,CR6,CR7,CARRY] in {
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 267 ENTRY(CR6) \
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| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 367 case PPC::CR6: RegNo = 6; break; in printcrbitm()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/InstPrinter/ |
| D | PPCInstPrinter.cpp | 410 case PPC::CR6: RegNo = 6; break; in printcrbitm()
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| /external/capstone/arch/X86/ |
| D | X86DisassemblerDecoder.h | 367 ENTRY(CR6) \
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 361 ENTRY(CR6) \
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 361 ENTRY(CR6) \
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 217 case X86::CR6: case X86::CR14: case X86::DR6: return 6; in getX86RegNum()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 36 CR6 = 17,
265 const unsigned CR6_Overlaps[] = { X86::CR6, 0 };
582 { "CR6", CR6_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
800 …X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9…
1449 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false );
1610 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false );
1771 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, false );
1937 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true );
2098 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true );
2259 RI->mapLLVMRegToDwarfReg(X86::CR6, -1, true );
[all …]
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| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
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| /external/swiftshader/third_party/LLVM/include/llvm/ |
| D | IntrinsicsPowerPC.td | 186 // Predicate Comparisons. The first operand specifies interpretation of CR6.
|