1//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Altivec extension to the PowerPC instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// *********************************** NOTE *********************************** 15// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 16// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 17// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 18// ** whether lanes are numbered from left to right. An instruction like ** 19// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 20// ** relies only on the corresponding lane of the source vectors. However, ** 21// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 22// ** "odd" lanes are different for big-endian and little-endian numbering. ** 23// ** ** 24// ** When adding new VMX and VSX instructions, please consider whether they ** 25// ** are lane-sensitive. If so, they must be added to a switch statement ** 26// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 27// **************************************************************************** 28 29 30//===----------------------------------------------------------------------===// 31// Altivec transformation functions and pattern fragments. 32// 33 34// Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 35// of that type. 36def vnot_ppc : PatFrag<(ops node:$in), 37 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 38 39def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 40 (vector_shuffle node:$lhs, node:$rhs), [{ 41 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 42}]>; 43def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 44 (vector_shuffle node:$lhs, node:$rhs), [{ 45 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 46}]>; 47def vpkudum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 48 (vector_shuffle node:$lhs, node:$rhs), [{ 49 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 0, *CurDAG); 50}]>; 51def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 52 (vector_shuffle node:$lhs, node:$rhs), [{ 53 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 54}]>; 55def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 56 (vector_shuffle node:$lhs, node:$rhs), [{ 57 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 58}]>; 59def vpkudum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 60 (vector_shuffle node:$lhs, node:$rhs), [{ 61 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 1, *CurDAG); 62}]>; 63 64// These fragments are provided for little-endian, where the inputs must be 65// swapped for correct semantics. 66def vpkuhum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 67 (vector_shuffle node:$lhs, node:$rhs), [{ 68 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 69}]>; 70def vpkuwum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 71 (vector_shuffle node:$lhs, node:$rhs), [{ 72 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 73}]>; 74def vpkudum_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 75 (vector_shuffle node:$lhs, node:$rhs), [{ 76 return PPC::isVPKUDUMShuffleMask(cast<ShuffleVectorSDNode>(N), 2, *CurDAG); 77}]>; 78 79def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 81 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 82}]>; 83def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 85 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 86}]>; 87def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 89 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 90}]>; 91def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 92 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 93 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG); 94}]>; 95def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 96 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 97 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG); 98}]>; 99def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 101 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG); 102}]>; 103 104 105def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 106 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 107 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 108}]>; 109def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 110 (vector_shuffle node:$lhs, node:$rhs), [{ 111 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 112}]>; 113def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 114 (vector_shuffle node:$lhs, node:$rhs), [{ 115 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 116}]>; 117def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG); 120}]>; 121def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 122 (vector_shuffle node:$lhs, node:$rhs), [{ 123 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG); 124}]>; 125def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 126 (vector_shuffle node:$lhs, node:$rhs), [{ 127 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG); 128}]>; 129 130 131// These fragments are provided for little-endian, where the inputs must be 132// swapped for correct semantics. 133def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 134 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 135 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 136}]>; 137def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 138 (vector_shuffle node:$lhs, node:$rhs), [{ 139 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 140}]>; 141def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 142 (vector_shuffle node:$lhs, node:$rhs), [{ 143 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 144}]>; 145def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 146 (vector_shuffle node:$lhs, node:$rhs), [{ 147 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG); 148}]>; 149def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 150 (vector_shuffle node:$lhs, node:$rhs), [{ 151 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG); 152}]>; 153def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 154 (vector_shuffle node:$lhs, node:$rhs), [{ 155 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG); 156}]>; 157 158 159def vmrgew_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 160 (vector_shuffle node:$lhs, node:$rhs), [{ 161 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 0, *CurDAG); 162}]>; 163def vmrgow_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 164 (vector_shuffle node:$lhs, node:$rhs), [{ 165 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 0, *CurDAG); 166}]>; 167def vmrgew_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 168 (vector_shuffle node:$lhs, node:$rhs), [{ 169 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 1, *CurDAG); 170}]>; 171def vmrgow_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 172 (vector_shuffle node:$lhs, node:$rhs), [{ 173 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 1, *CurDAG); 174}]>; 175def vmrgew_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 176 (vector_shuffle node:$lhs, node:$rhs), [{ 177 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), true, 2, *CurDAG); 178}]>; 179def vmrgow_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 180 (vector_shuffle node:$lhs, node:$rhs), [{ 181 return PPC::isVMRGEOShuffleMask(cast<ShuffleVectorSDNode>(N), false, 2, *CurDAG); 182}]>; 183 184 185 186def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 187 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 0, *CurDAG), SDLoc(N)); 188}]>; 189def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 190 (vector_shuffle node:$lhs, node:$rhs), [{ 191 return PPC::isVSLDOIShuffleMask(N, 0, *CurDAG) != -1; 192}], VSLDOI_get_imm>; 193 194 195/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 196/// vector_shuffle(X,undef,mask) by the dag combiner. 197def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 198 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 1, *CurDAG), SDLoc(N)); 199}]>; 200def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 201 (vector_shuffle node:$lhs, node:$rhs), [{ 202 return PPC::isVSLDOIShuffleMask(N, 1, *CurDAG) != -1; 203}], VSLDOI_unary_get_imm>; 204 205 206/// VSLDOI_swapped* - These fragments are provided for little-endian, where 207/// the inputs must be swapped for correct semantics. 208def VSLDOI_swapped_get_imm : SDNodeXForm<vector_shuffle, [{ 209 return getI32Imm(PPC::isVSLDOIShuffleMask(N, 2, *CurDAG), SDLoc(N)); 210}]>; 211def vsldoi_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 212 (vector_shuffle node:$lhs, node:$rhs), [{ 213 return PPC::isVSLDOIShuffleMask(N, 2, *CurDAG) != -1; 214}], VSLDOI_get_imm>; 215 216 217// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 218def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 219 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG), SDLoc(N)); 220}]>; 221def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 222 (vector_shuffle node:$lhs, node:$rhs), [{ 223 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 224}], VSPLTB_get_imm>; 225def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 226 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG), SDLoc(N)); 227}]>; 228def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 229 (vector_shuffle node:$lhs, node:$rhs), [{ 230 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 231}], VSPLTH_get_imm>; 232def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 233 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG), SDLoc(N)); 234}]>; 235def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 236 (vector_shuffle node:$lhs, node:$rhs), [{ 237 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 238}], VSPLTW_get_imm>; 239 240 241// VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 242def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 243 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 244}]>; 245def vecspltisb : PatLeaf<(build_vector), [{ 246 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != nullptr; 247}], VSPLTISB_get_imm>; 248 249// VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 250def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 251 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 252}]>; 253def vecspltish : PatLeaf<(build_vector), [{ 254 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != nullptr; 255}], VSPLTISH_get_imm>; 256 257// VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 258def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 259 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 260}]>; 261def vecspltisw : PatLeaf<(build_vector), [{ 262 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; 263}], VSPLTISW_get_imm>; 264 265//===----------------------------------------------------------------------===// 266// Helpers for defining instructions that directly correspond to intrinsics. 267 268// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. 269class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> 270 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 271 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 272 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; 273 274// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the 275// inputs doesn't match the type of the output. 276class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 277 ValueType InTy> 278 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 279 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 280 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; 281 282// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two 283// input types and an output type. 284class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, 285 ValueType In1Ty, ValueType In2Ty> 286 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 287 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP, 288 [(set OutTy:$vD, 289 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; 290 291// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. 292class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 293 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 294 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 295 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; 296 297// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the 298// inputs doesn't match the type of the output. 299class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 300 ValueType InTy> 301 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 302 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 303 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; 304 305// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two 306// input types and an output type. 307class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 308 ValueType In1Ty, ValueType In2Ty> 309 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 310 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, 311 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; 312 313// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. 314class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> 315 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 316 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 317 [(set v4f32:$vD, (IntID v4f32:$vB))]>; 318 319// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the 320// inputs doesn't match the type of the output. 321class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, 322 ValueType InTy> 323 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), 324 !strconcat(opc, " $vD, $vB"), IIC_VecFP, 325 [(set OutTy:$vD, (IntID InTy:$vB))]>; 326 327class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 328 : VXForm_BX<xo, (outs vrrc:$vD), (ins vrrc:$vA), 329 !strconcat(opc, " $vD, $vA"), IIC_VecFP, 330 [(set Ty:$vD, (IntID Ty:$vA))]>; 331 332class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> 333 : VXForm_CR<xo, (outs vrrc:$vD), (ins vrrc:$vA, u1imm:$ST, u4imm:$SIX), 334 !strconcat(opc, " $vD, $vA, $ST, $SIX"), IIC_VecFP, 335 [(set Ty:$vD, (IntID Ty:$vA, imm:$ST, imm:$SIX))]>; 336 337//===----------------------------------------------------------------------===// 338// Instruction Definitions. 339 340def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">; 341let Predicates = [HasAltivec] in { 342 343def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), 344 "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, 345 Deprecated<DeprecatedDST> { 346 let A = 0; 347 let B = 0; 348} 349 350def DSSALL : DSS_Form<1, 822, (outs), (ins), 351 "dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>, 352 Deprecated<DeprecatedDST> { 353 let STRM = 0; 354 let A = 0; 355 let B = 0; 356} 357 358def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 359 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 360 [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, 361 Deprecated<DeprecatedDST>; 362 363def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 364 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 365 [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, 366 Deprecated<DeprecatedDST>; 367 368def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 369 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 370 [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, 371 Deprecated<DeprecatedDST>; 372 373def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), 374 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 375 [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, 376 Deprecated<DeprecatedDST>; 377 378let isCodeGenOnly = 1 in { 379 // The very same instructions as above, but formally matching 64bit registers. 380 def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 381 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 382 [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, 383 Deprecated<DeprecatedDST>; 384 385 def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 386 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 387 [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, 388 Deprecated<DeprecatedDST>; 389 390 def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 391 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 392 [(int_ppc_altivec_dstst i64:$rA, i32:$rB, 393 imm:$STRM)]>, 394 Deprecated<DeprecatedDST>; 395 396 def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), 397 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, 398 [(int_ppc_altivec_dststt i64:$rA, i32:$rB, 399 imm:$STRM)]>, 400 Deprecated<DeprecatedDST>; 401} 402 403def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), 404 "mfvscr $vD", IIC_LdStStore, 405 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; 406def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), 407 "mtvscr $vB", IIC_LdStLoad, 408 [(int_ppc_altivec_mtvscr v4i32:$vB)]>; 409 410let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. 411def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), 412 "lvebx $vD, $src", IIC_LdStLoad, 413 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 414def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), 415 "lvehx $vD, $src", IIC_LdStLoad, 416 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 417def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), 418 "lvewx $vD, $src", IIC_LdStLoad, 419 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 420def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), 421 "lvx $vD, $src", IIC_LdStLoad, 422 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 423def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), 424 "lvxl $vD, $src", IIC_LdStLoad, 425 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 426} 427 428def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), 429 "lvsl $vD, $src", IIC_LdStLoad, 430 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 431 PPC970_Unit_LSU; 432def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), 433 "lvsr $vD, $src", IIC_LdStLoad, 434 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 435 PPC970_Unit_LSU; 436 437let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. 438def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), 439 "stvebx $rS, $dst", IIC_LdStStore, 440 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; 441def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), 442 "stvehx $rS, $dst", IIC_LdStStore, 443 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; 444def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), 445 "stvewx $rS, $dst", IIC_LdStStore, 446 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; 447def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), 448 "stvx $rS, $dst", IIC_LdStStore, 449 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; 450def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), 451 "stvxl $rS, $dst", IIC_LdStStore, 452 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; 453} 454 455let PPC970_Unit = 5 in { // VALU Operations. 456// VA-Form instructions. 3-input AltiVec ops. 457let isCommutable = 1 in { 458def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 459 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, 460 [(set v4f32:$vD, 461 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; 462 463// FIXME: The fma+fneg pattern won't match because fneg is not legal. 464def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), 465 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, 466 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, 467 (fneg v4f32:$vB))))]>; 468 469def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; 470def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, 471 v8i16>; 472def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>; 473} // isCommutable 474 475def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm, 476 v4i32, v4i32, v16i8>; 477def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; 478 479// Shuffles. 480def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), 481 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, 482 [(set v16i8:$vD, 483 (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; 484 485// VX-Form instructions. AltiVec arithmetic ops. 486let isCommutable = 1 in { 487def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 488 "vaddfp $vD, $vA, $vB", IIC_VecFP, 489 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; 490 491def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 492 "vaddubm $vD, $vA, $vB", IIC_VecGeneral, 493 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; 494def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 495 "vadduhm $vD, $vA, $vB", IIC_VecGeneral, 496 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; 497def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 498 "vadduwm $vD, $vA, $vB", IIC_VecGeneral, 499 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; 500 501def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; 502def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; 503def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>; 504def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>; 505def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>; 506def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>; 507def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>; 508} // isCommutable 509 510let isCommutable = 1 in 511def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 512 "vand $vD, $vA, $vB", IIC_VecFP, 513 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; 514def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 515 "vandc $vD, $vA, $vB", IIC_VecFP, 516 [(set v4i32:$vD, (and v4i32:$vA, 517 (vnot_ppc v4i32:$vB)))]>; 518 519def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 520 "vcfsx $vD, $vB, $UIMM", IIC_VecFP, 521 [(set v4f32:$vD, 522 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; 523def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 524 "vcfux $vD, $vB, $UIMM", IIC_VecFP, 525 [(set v4f32:$vD, 526 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; 527def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 528 "vctsxs $vD, $vB, $UIMM", IIC_VecFP, 529 [(set v4i32:$vD, 530 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; 531def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 532 "vctuxs $vD, $vB, $UIMM", IIC_VecFP, 533 [(set v4i32:$vD, 534 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; 535 536// Defines with the UIM field set to 0 for floating-point 537// to integer (fp_to_sint/fp_to_uint) conversions and integer 538// to floating-point (sint_to_fp/uint_to_fp) conversions. 539let isCodeGenOnly = 1, VA = 0 in { 540def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), 541 "vcfsx $vD, $vB, 0", IIC_VecFP, 542 [(set v4f32:$vD, 543 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; 544def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), 545 "vctuxs $vD, $vB, 0", IIC_VecFP, 546 [(set v4i32:$vD, 547 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; 548def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), 549 "vcfux $vD, $vB, 0", IIC_VecFP, 550 [(set v4f32:$vD, 551 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; 552def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), 553 "vctsxs $vD, $vB, 0", IIC_VecFP, 554 [(set v4i32:$vD, 555 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; 556} 557def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; 558def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; 559 560let isCommutable = 1 in { 561def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>; 562def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>; 563def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>; 564def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>; 565def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>; 566def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>; 567 568def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>; 569def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>; 570def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>; 571def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>; 572def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>; 573def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>; 574def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>; 575def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>; 576def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>; 577def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>; 578def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>; 579def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>; 580def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>; 581def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; 582} // isCommutable 583 584def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 585 "vmrghb $vD, $vA, $vB", IIC_VecFP, 586 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; 587def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 588 "vmrghh $vD, $vA, $vB", IIC_VecFP, 589 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; 590def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 591 "vmrghw $vD, $vA, $vB", IIC_VecFP, 592 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; 593def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 594 "vmrglb $vD, $vA, $vB", IIC_VecFP, 595 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; 596def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 597 "vmrglh $vD, $vA, $vB", IIC_VecFP, 598 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; 599def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 600 "vmrglw $vD, $vA, $vB", IIC_VecFP, 601 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; 602 603def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, 604 v4i32, v16i8, v4i32>; 605def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm, 606 v4i32, v8i16, v4i32>; 607def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs, 608 v4i32, v8i16, v4i32>; 609def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm, 610 v4i32, v16i8, v4i32>; 611def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm, 612 v4i32, v8i16, v4i32>; 613def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs, 614 v4i32, v8i16, v4i32>; 615 616let isCommutable = 1 in { 617def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb, 618 v8i16, v16i8>; 619def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh, 620 v4i32, v8i16>; 621def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub, 622 v8i16, v16i8>; 623def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh, 624 v4i32, v8i16>; 625def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb, 626 v8i16, v16i8>; 627def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh, 628 v4i32, v8i16>; 629def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub, 630 v8i16, v16i8>; 631def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh, 632 v4i32, v8i16>; 633} // isCommutable 634 635def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>; 636def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>; 637def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>; 638def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>; 639def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>; 640def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 641 642def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; 643 644def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 645 "vsubfp $vD, $vA, $vB", IIC_VecGeneral, 646 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; 647def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 648 "vsububm $vD, $vA, $vB", IIC_VecGeneral, 649 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; 650def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 651 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, 652 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; 653def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 654 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, 655 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; 656 657def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; 658def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; 659def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>; 660def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>; 661def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>; 662def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>; 663 664def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>; 665def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>; 666 667def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs, 668 v4i32, v16i8, v4i32>; 669def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs, 670 v4i32, v8i16, v4i32>; 671def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs, 672 v4i32, v16i8, v4i32>; 673 674def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 675 "vnor $vD, $vA, $vB", IIC_VecFP, 676 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, 677 v4i32:$vB)))]>; 678let isCommutable = 1 in { 679def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 680 "vor $vD, $vA, $vB", IIC_VecFP, 681 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; 682def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 683 "vxor $vD, $vA, $vB", IIC_VecFP, 684 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; 685} // isCommutable 686 687def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; 688def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>; 689def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>; 690 691def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >; 692def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>; 693 694def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>; 695def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; 696def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; 697 698def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 699 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, 700 [(set v16i8:$vD, 701 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; 702def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 703 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, 704 [(set v16i8:$vD, 705 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; 706def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), 707 "vspltw $vD, $vB, $UIMM", IIC_VecPerm, 708 [(set v16i8:$vD, 709 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; 710let isCodeGenOnly = 1 in { 711 def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 712 "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; 713 def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), 714 "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; 715} 716 717def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; 718def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>; 719 720def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>; 721def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>; 722def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>; 723def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>; 724def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>; 725def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; 726 727 728def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), 729 "vspltisb $vD, $SIMM", IIC_VecPerm, 730 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; 731def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), 732 "vspltish $vD, $SIMM", IIC_VecPerm, 733 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; 734def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), 735 "vspltisw $vD, $SIMM", IIC_VecPerm, 736 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; 737 738// Vector Pack. 739def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, 740 v8i16, v4i32>; 741def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss, 742 v16i8, v8i16>; 743def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus, 744 v16i8, v8i16>; 745def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss, 746 v8i16, v4i32>; 747def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, 748 v8i16, v4i32>; 749def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 750 "vpkuhum $vD, $vA, $vB", IIC_VecFP, 751 [(set v16i8:$vD, 752 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; 753def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, 754 v16i8, v8i16>; 755def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 756 "vpkuwum $vD, $vA, $vB", IIC_VecFP, 757 [(set v16i8:$vD, 758 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; 759def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, 760 v8i16, v4i32>; 761 762// Vector Unpack. 763def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, 764 v4i32, v8i16>; 765def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb, 766 v8i16, v16i8>; 767def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh, 768 v4i32, v8i16>; 769def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx, 770 v4i32, v8i16>; 771def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb, 772 v8i16, v16i8>; 773def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh, 774 v4i32, v8i16>; 775 776 777// Altivec Comparisons. 778 779class VCMP<bits<10> xo, string asmstr, ValueType Ty> 780 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 781 IIC_VecFPCompare, 782 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; 783class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 784 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr, 785 IIC_VecFPCompare, 786 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { 787 let Defs = [CR6]; 788 let RC = 1; 789} 790 791// f32 element comparisons.0 792def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 793def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 794def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 795def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 796def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 797def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 798def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 799def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 800 801// i8 element comparisons. 802def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 803def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 804def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 805def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 806def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 807def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 808 809// i16 element comparisons. 810def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 811def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 812def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 813def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 814def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 815def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 816 817// i32 element comparisons. 818def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 819def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 820def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 821def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 822def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 823def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 824 825let isCodeGenOnly = 1 in { 826def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 827 "vxor $vD, $vD, $vD", IIC_VecFP, 828 [(set v16i8:$vD, (v16i8 immAllZerosV))]>; 829def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 830 "vxor $vD, $vD, $vD", IIC_VecFP, 831 [(set v8i16:$vD, (v8i16 immAllZerosV))]>; 832def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), 833 "vxor $vD, $vD, $vD", IIC_VecFP, 834 [(set v4i32:$vD, (v4i32 immAllZerosV))]>; 835 836let IMM=-1 in { 837def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), 838 "vspltisw $vD, -1", IIC_VecFP, 839 [(set v16i8:$vD, (v16i8 immAllOnesV))]>; 840def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), 841 "vspltisw $vD, -1", IIC_VecFP, 842 [(set v8i16:$vD, (v8i16 immAllOnesV))]>; 843def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), 844 "vspltisw $vD, -1", IIC_VecFP, 845 [(set v4i32:$vD, (v4i32 immAllOnesV))]>; 846} 847} 848} // VALU Operations. 849 850//===----------------------------------------------------------------------===// 851// Additional Altivec Patterns 852// 853 854// Extended mnemonics 855def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 856def : InstAlias<"vnot $vD, $vA", (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; 857 858// Loads. 859def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 860 861// Stores. 862def : Pat<(store v4i32:$rS, xoaddr:$dst), 863 (STVX $rS, xoaddr:$dst)>; 864 865// Bit conversions. 866def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 867def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 868def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 869def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; 870def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; 871 872def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 873def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 874def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 875def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; 876def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; 877 878def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 879def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 880def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 881def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; 882def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; 883 884def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 885def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 886def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 887def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; 888def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; 889 890def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; 891def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; 892def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; 893def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; 894def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; 895 896def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; 897def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; 898def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; 899def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; 900def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; 901 902// Shuffles. 903 904// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 905def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef), 906 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>; 907def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef), 908 (VPKUWUM $vA, $vA)>; 909def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef), 910 (VPKUHUM $vA, $vA)>; 911def:Pat<(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB), 912 (VSLDOI v16i8:$vA, v16i8:$vB, (VSLDOI_get_imm $SH))>; 913 914 915// Match vsldoi(y,x), vpkuwum(y,x), vpkuhum(y,x), i.e., swapped operands. 916// These fragments are matched for little-endian, where the inputs must 917// be swapped for correct semantics. 918def:Pat<(vsldoi_swapped_shuffle:$in v16i8:$vA, v16i8:$vB), 919 (VSLDOI $vB, $vA, (VSLDOI_swapped_get_imm $in))>; 920def:Pat<(vpkuwum_swapped_shuffle v16i8:$vA, v16i8:$vB), 921 (VPKUWUM $vB, $vA)>; 922def:Pat<(vpkuhum_swapped_shuffle v16i8:$vA, v16i8:$vB), 923 (VPKUHUM $vB, $vA)>; 924 925// Match vmrg*(x,x) 926def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef), 927 (VMRGLB $vA, $vA)>; 928def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef), 929 (VMRGLH $vA, $vA)>; 930def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef), 931 (VMRGLW $vA, $vA)>; 932def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef), 933 (VMRGHB $vA, $vA)>; 934def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef), 935 (VMRGHH $vA, $vA)>; 936def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef), 937 (VMRGHW $vA, $vA)>; 938 939// Match vmrg*(y,x), i.e., swapped operands. These fragments 940// are matched for little-endian, where the inputs must be 941// swapped for correct semantics. 942def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB), 943 (VMRGLB $vB, $vA)>; 944def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB), 945 (VMRGLH $vB, $vA)>; 946def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB), 947 (VMRGLW $vB, $vA)>; 948def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB), 949 (VMRGHB $vB, $vA)>; 950def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB), 951 (VMRGHH $vB, $vA)>; 952def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB), 953 (VMRGHW $vB, $vA)>; 954 955// Logical Operations 956def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>; 957 958def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)), 959 (VNOR $A, $B)>; 960def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)), 961 (VANDC $A, $B)>; 962 963def : Pat<(fmul v4f32:$vA, v4f32:$vB), 964 (VMADDFP $vA, $vB, 965 (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 966 967// Fused multiply add and multiply sub for packed float. These are represented 968// separately from the real instructions above, for operations that must have 969// the additional precision, such as Newton-Rhapson (used by divide, sqrt) 970def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 971 (VMADDFP $A, $B, $C)>; 972def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 973 (VNMSUBFP $A, $B, $C)>; 974 975def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C), 976 (VMADDFP $A, $B, $C)>; 977def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C), 978 (VNMSUBFP $A, $B, $C)>; 979 980def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), 981 (VPERM $vA, $vB, $vC)>; 982 983def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; 984def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; 985 986// Vector shifts 987def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)), 988 (v16i8 (VSLB $vA, $vB))>; 989def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)), 990 (v8i16 (VSLH $vA, $vB))>; 991def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)), 992 (v4i32 (VSLW $vA, $vB))>; 993def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)), 994 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 995def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)), 996 (v16i8 (VSLB $vA, $vB))>; 997def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)), 998 (v8i16 (VSLH $vA, $vB))>; 999def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)), 1000 (v4i32 (VSLW $vA, $vB))>; 1001def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)), 1002 (v1i128 (VSL (v16i8 (VSLO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1003 1004def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)), 1005 (v16i8 (VSRB $vA, $vB))>; 1006def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)), 1007 (v8i16 (VSRH $vA, $vB))>; 1008def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)), 1009 (v4i32 (VSRW $vA, $vB))>; 1010def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)), 1011 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1012def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)), 1013 (v16i8 (VSRB $vA, $vB))>; 1014def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)), 1015 (v8i16 (VSRH $vA, $vB))>; 1016def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)), 1017 (v4i32 (VSRW $vA, $vB))>; 1018def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)), 1019 (v1i128 (VSR (v16i8 (VSRO $vA, $vB)), (v16i8 (VSPLTB 15, $vB))))>; 1020 1021def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)), 1022 (v16i8 (VSRAB $vA, $vB))>; 1023def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)), 1024 (v8i16 (VSRAH $vA, $vB))>; 1025def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)), 1026 (v4i32 (VSRAW $vA, $vB))>; 1027def : Pat<(v16i8 (PPCsra v16i8:$vA, v16i8:$vB)), 1028 (v16i8 (VSRAB $vA, $vB))>; 1029def : Pat<(v8i16 (PPCsra v8i16:$vA, v8i16:$vB)), 1030 (v8i16 (VSRAH $vA, $vB))>; 1031def : Pat<(v4i32 (PPCsra v4i32:$vA, v4i32:$vB)), 1032 (v4i32 (VSRAW $vA, $vB))>; 1033 1034// Float to integer and integer to float conversions 1035def : Pat<(v4i32 (fp_to_sint v4f32:$vA)), 1036 (VCTSXS_0 $vA)>; 1037def : Pat<(v4i32 (fp_to_uint v4f32:$vA)), 1038 (VCTUXS_0 $vA)>; 1039def : Pat<(v4f32 (sint_to_fp v4i32:$vA)), 1040 (VCFSX_0 $vA)>; 1041def : Pat<(v4f32 (uint_to_fp v4i32:$vA)), 1042 (VCFUX_0 $vA)>; 1043 1044// Floating-point rounding 1045def : Pat<(v4f32 (ffloor v4f32:$vA)), 1046 (VRFIM $vA)>; 1047def : Pat<(v4f32 (fceil v4f32:$vA)), 1048 (VRFIP $vA)>; 1049def : Pat<(v4f32 (ftrunc v4f32:$vA)), 1050 (VRFIZ $vA)>; 1051def : Pat<(v4f32 (fnearbyint v4f32:$vA)), 1052 (VRFIN $vA)>; 1053 1054} // end HasAltivec 1055 1056def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; 1057def HasP8Crypto : Predicate<"PPCSubTarget->hasP8Crypto()">; 1058let Predicates = [HasP8Altivec] in { 1059 1060let isCommutable = 1 in { 1061def VMULESW : VX1_Int_Ty2<904, "vmulesw", int_ppc_altivec_vmulesw, 1062 v2i64, v4i32>; 1063def VMULEUW : VX1_Int_Ty2<648, "vmuleuw", int_ppc_altivec_vmuleuw, 1064 v2i64, v4i32>; 1065def VMULOSW : VX1_Int_Ty2<392, "vmulosw", int_ppc_altivec_vmulosw, 1066 v2i64, v4i32>; 1067def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, 1068 v2i64, v4i32>; 1069def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1070 "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, 1071 [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; 1072def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; 1073def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; 1074def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; 1075def VMINUD : VX1_Int_Ty<706, "vminud", int_ppc_altivec_vminud, v2i64>; 1076} // isCommutable 1077 1078// Vector merge 1079def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1080 "vmrgew $vD, $vA, $vB", IIC_VecFP, 1081 [(set v16i8:$vD, 1082 (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; 1083def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1084 "vmrgow $vD, $vA, $vB", IIC_VecFP, 1085 [(set v16i8:$vD, 1086 (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; 1087 1088// Match vmrgew(x,x) and vmrgow(x,x) 1089def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), 1090 (VMRGEW $vA, $vA)>; 1091def:Pat<(vmrgow_unary_shuffle v16i8:$vA, undef), 1092 (VMRGOW $vA, $vA)>; 1093 1094// Match vmrgew(y,x) and vmrgow(y,x), i.e., swapped operands. These fragments 1095// are matched for little-endian, where the inputs must be swapped for correct 1096// semantics.w 1097def:Pat<(vmrgew_swapped_shuffle v16i8:$vA, v16i8:$vB), 1098 (VMRGEW $vB, $vA)>; 1099def:Pat<(vmrgow_swapped_shuffle v16i8:$vA, v16i8:$vB), 1100 (VMRGOW $vB, $vA)>; 1101 1102 1103// Vector shifts 1104def VRLD : VX1_Int_Ty<196, "vrld", int_ppc_altivec_vrld, v2i64>; 1105def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1106 "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; 1107def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1108 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; 1109def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1110 "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; 1111 1112def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), 1113 (v2i64 (VSLD $vA, $vB))>; 1114def : Pat<(v2i64 (PPCshl v2i64:$vA, v2i64:$vB)), 1115 (v2i64 (VSLD $vA, $vB))>; 1116def : Pat<(v2i64 (srl v2i64:$vA, v2i64:$vB)), 1117 (v2i64 (VSRD $vA, $vB))>; 1118def : Pat<(v2i64 (PPCsrl v2i64:$vA, v2i64:$vB)), 1119 (v2i64 (VSRD $vA, $vB))>; 1120def : Pat<(v2i64 (sra v2i64:$vA, v2i64:$vB)), 1121 (v2i64 (VSRAD $vA, $vB))>; 1122def : Pat<(v2i64 (PPCsra v2i64:$vA, v2i64:$vB)), 1123 (v2i64 (VSRAD $vA, $vB))>; 1124 1125// Vector Integer Arithmetic Instructions 1126let isCommutable = 1 in { 1127def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1128 "vaddudm $vD, $vA, $vB", IIC_VecGeneral, 1129 [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; 1130def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1131 "vadduqm $vD, $vA, $vB", IIC_VecGeneral, 1132 [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; 1133} // isCommutable 1134 1135// Vector Quadword Add 1136def VADDEUQM : VA1a_Int_Ty<60, "vaddeuqm", int_ppc_altivec_vaddeuqm, v1i128>; 1137def VADDCUQ : VX1_Int_Ty<320, "vaddcuq", int_ppc_altivec_vaddcuq, v1i128>; 1138def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; 1139 1140// Vector Doubleword Subtract 1141def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1142 "vsubudm $vD, $vA, $vB", IIC_VecGeneral, 1143 [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; 1144 1145// Vector Quadword Subtract 1146def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1147 "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, 1148 [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; 1149def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; 1150def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; 1151def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; 1152 1153// Count Leading Zeros 1154def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), 1155 "vclzb $vD, $vB", IIC_VecGeneral, 1156 [(set v16i8:$vD, (ctlz v16i8:$vB))]>; 1157def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), 1158 "vclzh $vD, $vB", IIC_VecGeneral, 1159 [(set v8i16:$vD, (ctlz v8i16:$vB))]>; 1160def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), 1161 "vclzw $vD, $vB", IIC_VecGeneral, 1162 [(set v4i32:$vD, (ctlz v4i32:$vB))]>; 1163def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), 1164 "vclzd $vD, $vB", IIC_VecGeneral, 1165 [(set v2i64:$vD, (ctlz v2i64:$vB))]>; 1166 1167// Population Count 1168def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), 1169 "vpopcntb $vD, $vB", IIC_VecGeneral, 1170 [(set v16i8:$vD, (ctpop v16i8:$vB))]>; 1171def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), 1172 "vpopcnth $vD, $vB", IIC_VecGeneral, 1173 [(set v8i16:$vD, (ctpop v8i16:$vB))]>; 1174def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), 1175 "vpopcntw $vD, $vB", IIC_VecGeneral, 1176 [(set v4i32:$vD, (ctpop v4i32:$vB))]>; 1177def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), 1178 "vpopcntd $vD, $vB", IIC_VecGeneral, 1179 [(set v2i64:$vD, (ctpop v2i64:$vB))]>; 1180 1181let isCommutable = 1 in { 1182// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 1183// VSX equivalents. We need to fix this up at some point. Two possible 1184// solutions for this problem: 1185// 1. Disable Altivec patterns that compete with VSX patterns using the 1186// !HasVSX predicate. This essentially favours VSX over Altivec, in 1187// hopes of reducing register pressure (larger register set using VSX 1188// instructions than VMX instructions) 1189// 2. Employ a more disciplined use of AddedComplexity, which would provide 1190// more fine-grained control than option 1. This would be beneficial 1191// if we find situations where Altivec is really preferred over VSX. 1192def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1193 "veqv $vD, $vA, $vB", IIC_VecGeneral, 1194 [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>; 1195def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1196 "vnand $vD, $vA, $vB", IIC_VecGeneral, 1197 [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>; 1198} // isCommutable 1199 1200def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1201 "vorc $vD, $vA, $vB", IIC_VecGeneral, 1202 [(set v4i32:$vD, (or v4i32:$vA, 1203 (vnot_ppc v4i32:$vB)))]>; 1204 1205// i64 element comparisons. 1206def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; 1207def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>; 1208def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; 1209def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; 1210def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; 1211def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; 1212 1213// The cryptography instructions that do not require Category:Vector.Crypto 1214def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", 1215 int_ppc_altivec_crypto_vpmsumb, v16i8>; 1216def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh", 1217 int_ppc_altivec_crypto_vpmsumh, v8i16>; 1218def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw", 1219 int_ppc_altivec_crypto_vpmsumw, v4i32>; 1220def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", 1221 int_ppc_altivec_crypto_vpmsumd, v2i64>; 1222def VPERMXOR : VA1a_Int_Ty<45, "vpermxor", 1223 int_ppc_altivec_crypto_vpermxor, v16i8>; 1224 1225// Vector doubleword integer pack and unpack. 1226def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss, 1227 v4i32, v2i64>; 1228def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus, 1229 v4i32, v2i64>; 1230def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1231 "vpkudum $vD, $vA, $vB", IIC_VecFP, 1232 [(set v16i8:$vD, 1233 (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; 1234def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, 1235 v4i32, v2i64>; 1236def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, 1237 v2i64, v4i32>; 1238def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, 1239 v2i64, v4i32>; 1240 1241// Shuffle patterns for unary and swapped (LE) vector pack modulo. 1242def:Pat<(vpkudum_unary_shuffle v16i8:$vA, undef), 1243 (VPKUDUM $vA, $vA)>; 1244def:Pat<(vpkudum_swapped_shuffle v16i8:$vA, v16i8:$vB), 1245 (VPKUDUM $vB, $vA)>; 1246 1247def VGBBD : VX2_Int_Ty2<1292, "vgbbd", int_ppc_altivec_vgbbd, v16i8, v16i8>; 1248def VBPERMQ : VX1_Int_Ty2<1356, "vbpermq", int_ppc_altivec_vbpermq, 1249 v2i64, v16i8>; 1250} // end HasP8Altivec 1251 1252// Crypto instructions (from builtins) 1253let Predicates = [HasP8Crypto] in { 1254def VSHASIGMAW : VXCR_Int_Ty<1666, "vshasigmaw", 1255 int_ppc_altivec_crypto_vshasigmaw, v4i32>; 1256def VSHASIGMAD : VXCR_Int_Ty<1730, "vshasigmad", 1257 int_ppc_altivec_crypto_vshasigmad, v2i64>; 1258def VCIPHER : VX1_Int_Ty<1288, "vcipher", int_ppc_altivec_crypto_vcipher, 1259 v2i64>; 1260def VCIPHERLAST : VX1_Int_Ty<1289, "vcipherlast", 1261 int_ppc_altivec_crypto_vcipherlast, v2i64>; 1262def VNCIPHER : VX1_Int_Ty<1352, "vncipher", 1263 int_ppc_altivec_crypto_vncipher, v2i64>; 1264def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast", 1265 int_ppc_altivec_crypto_vncipherlast, v2i64>; 1266def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>; 1267} // HasP8Crypto 1268 1269// The following altivec instructions were introduced in Power ISA 3.0 1270def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">; 1271let Predicates = [HasP9Altivec] in { 1272 1273// i8 element comparisons. 1274def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; 1275def VCMPNEBo : VCMPo < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; 1276def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; 1277def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; 1278 1279// i16 element comparisons. 1280def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; 1281def VCMPNEHo : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; 1282def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; 1283def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; 1284 1285// i32 element comparisons. 1286def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; 1287def VCMPNEWo : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; 1288def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; 1289def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; 1290 1291// VX-Form: [PO VRT / UIM VRB XO]. 1292// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent 1293// "/ UIM" (1 + 4 bit) 1294class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern> 1295 : VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB), 1296 !strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>; 1297 1298class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1299 : VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB), 1300 !strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>; 1301 1302// Vector Extract Unsigned 1303def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; 1304def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>; 1305def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>; 1306def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>; 1307 1308// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed 1309def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>; 1310def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>; 1311def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>; 1312def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>; 1313def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>; 1314def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>; 1315 1316// Vector Insert Element Instructions 1317def VINSERTB : VXForm_1<781, (outs vrrc:$vD), 1318 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1319 "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, 1320 [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, 1321 imm32SExt16:$UIM))]>, 1322 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1323def VINSERTH : VXForm_1<845, (outs vrrc:$vD), 1324 (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), 1325 "vinserth $vD, $vB, $UIM", IIC_VecGeneral, 1326 [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, 1327 imm32SExt16:$UIM))]>, 1328 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1329def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; 1330def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; 1331 1332class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1333 : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB), 1334 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1335class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern> 1336 : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB), 1337 !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>; 1338 1339// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] 1340def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), 1341 "vclzlsbb $rD, $vB", IIC_VecGeneral, 1342 [(set i32:$rD, (int_ppc_altivec_vclzlsbb 1343 v16i8:$vB))]>; 1344def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), 1345 "vctzlsbb $rD, $vB", IIC_VecGeneral, 1346 [(set i32:$rD, (int_ppc_altivec_vctzlsbb 1347 v16i8:$vB))]>; 1348// Vector Count Trailing Zeros 1349def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", 1350 [(set v16i8:$vD, (cttz v16i8:$vB))]>; 1351def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", 1352 [(set v8i16:$vD, (cttz v8i16:$vB))]>; 1353def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", 1354 [(set v4i32:$vD, (cttz v4i32:$vB))]>; 1355def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", 1356 [(set v2i64:$vD, (cttz v2i64:$vB))]>; 1357 1358// Vector Extend Sign 1359def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>; 1360def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>; 1361def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>; 1362def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>; 1363def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>; 1364let isCodeGenOnly = 1 in { 1365 def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; 1366 def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; 1367 def VEXTSB2Ds : VX_VT5_EO5_VB5s<1538, 24, "vextsb2d", []>; 1368 def VEXTSH2Ds : VX_VT5_EO5_VB5s<1538, 25, "vextsh2d", []>; 1369 def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>; 1370} 1371 1372// Vector Integer Negate 1373def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", 1374 [(set v4i32:$vD, 1375 (sub (v4i32 immAllZerosV), v4i32:$vB))]>; 1376 1377def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", 1378 [(set v2i64:$vD, 1379 (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), 1380 v2i64:$vB))]>; 1381 1382// Vector Parity Byte 1383def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, 1384 (int_ppc_altivec_vprtybw v4i32:$vB))]>; 1385def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, 1386 (int_ppc_altivec_vprtybd v2i64:$vB))]>; 1387def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, 1388 (int_ppc_altivec_vprtybq v1i128:$vB))]>; 1389 1390// Vector (Bit) Permute (Right-indexed) 1391def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1392 "vbpermd $vD, $vA, $vB", IIC_VecFP, []>; 1393def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), 1394 "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; 1395 1396class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> 1397 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1398 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; 1399 1400// Vector Rotate Left Mask/Mask-Insert 1401def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", 1402 [(set v4i32:$vD, 1403 (int_ppc_altivec_vrlwnm v4i32:$vA, 1404 v4i32:$vB))]>; 1405def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1406 "vrlwmi $vD, $vA, $vB", IIC_VecFP, 1407 [(set v4i32:$vD, 1408 (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, 1409 v4i32:$vDi))]>, 1410 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1411def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", 1412 [(set v2i64:$vD, 1413 (int_ppc_altivec_vrldnm v2i64:$vA, 1414 v2i64:$vB))]>; 1415def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), 1416 "vrldmi $vD, $vA, $vB", IIC_VecFP, 1417 [(set v2i64:$vD, 1418 (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, 1419 v2i64:$vDi))]>, 1420 RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; 1421 1422// Vector Shift Left/Right 1423def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", 1424 [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; 1425def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", 1426 [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; 1427 1428// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword 1429def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), 1430 "vmul10uq $vD, $vA", IIC_VecFP, []>; 1431def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), 1432 "vmul10cuq $vD, $vA", IIC_VecFP, []>; 1433 1434// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword 1435def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; 1436def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>; 1437 1438// Decimal Integer Format Conversion Instructions 1439 1440// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. 1441class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc, 1442 list<dag> pattern> 1443 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS), 1444 !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> { 1445 let Defs = [CR6]; 1446} 1447 1448// [PO VRT EO VRB 1 / XO] 1449class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc, 1450 list<dag> pattern> 1451 : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB), 1452 !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> { 1453 let Defs = [CR6]; 1454 let PS = 0; 1455} 1456 1457// Decimal Convert From/to National/Zoned/Signed-QWord 1458def BCDCFNo : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>; 1459def BCDCFZo : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>; 1460def BCDCTNo : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>; 1461def BCDCTZo : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>; 1462def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>; 1463def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; 1464 1465// Decimal Copy-Sign/Set-Sign 1466let Defs = [CR6] in 1467def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; 1468 1469def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; 1470 1471// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. 1472class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1473 : VX_RD5_RSp5_PS1_XO9<xo, 1474 (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS), 1475 !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> { 1476 let Defs = [CR6]; 1477} 1478 1479// [PO VRT VRA VRB 1 / XO] 1480class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern> 1481 : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1482 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> { 1483 let Defs = [CR6]; 1484 let PS = 0; 1485} 1486 1487// Decimal Shift/Unsigned-Shift/Shift-and-Round 1488def BCDSo : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; 1489def BCDUSo : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>; 1490def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; 1491 1492// Decimal (Unsigned) Truncate 1493def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; 1494def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; 1495 1496// Absolute Difference 1497def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1498 "vabsdub $vD, $vA, $vB", IIC_VecGeneral, 1499 [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; 1500def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1501 "vabsduh $vD, $vA, $vB", IIC_VecGeneral, 1502 [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; 1503def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), 1504 "vabsduw $vD, $vA, $vB", IIC_VecGeneral, 1505 [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; 1506 1507} // end HasP9Altivec 1508