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Searched refs:CTTZ (Results 1 – 25 of 87) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
108 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
131 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
132 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
154 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
108 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
131 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
132 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
154 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dffs-1.ll108 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
109 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
119 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
120 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
130 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
131 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dffs-1.ll151 ; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
152 ; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
167 ; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
168 ; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
183 ; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true), !range !1
184 ; TARGET-NEXT: [[TMP1:%.*]] = trunc i64 [[CTTZ]] to i32
Dadd2.ll332 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !0
333 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
354 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !1
355 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1628 { ISD::CTTZ, MVT::v8i64, 10 }, in getIntrinsicInstrCost()
1629 { ISD::CTTZ, MVT::v16i32, 14 }, in getIntrinsicInstrCost()
1630 { ISD::CTTZ, MVT::v32i16, 12 }, in getIntrinsicInstrCost()
1631 { ISD::CTTZ, MVT::v64i8, 9 }, in getIntrinsicInstrCost()
1640 { ISD::CTTZ, MVT::v8i64, 20 }, in getIntrinsicInstrCost()
1641 { ISD::CTTZ, MVT::v16i32, 28 }, in getIntrinsicInstrCost()
1673 { ISD::CTTZ, MVT::v4i64, 10 }, in getIntrinsicInstrCost()
1674 { ISD::CTTZ, MVT::v8i32, 14 }, in getIntrinsicInstrCost()
1675 { ISD::CTTZ, MVT::v16i16, 12 }, in getIntrinsicInstrCost()
1676 { ISD::CTTZ, MVT::v32i8, 9 }, in getIntrinsicInstrCost()
[all …]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h320 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h385 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp75 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in BlackfinTargetLowering()
114 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in BlackfinTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp346 case ISD::CTTZ: in LegalizeOp()
1133 if (TLI.isOperationLegalOrCustom(ISD::CTTZ, Op.getValueType())) { in ExpandCTTZ_ZERO_UNDEF()
1135 return DAG.getNode(ISD::CTTZ, DL, Op.getValueType(), Op.getOperand(0)); in ExpandCTTZ_ZERO_UNDEF()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp159 case ISD::CTTZ: in LegalizeOp()
DLegalizeIntegerTypes.cpp62 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult()
339 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); in PromoteIntRes_CTTZ()
1103 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
1735 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); in ExpandIntRes_CTTZ()
1736 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); in ExpandIntRes_CTTZ()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp111 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in SystemZTargetLowering()
112 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in SystemZTargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp90 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
146 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
1462 case ISD::CTTZ: in LowerHvxOperation()
1492 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp287 case ISD::CTTZ: in LegalizeOp()
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ; in ExpandCTLZ_CTTZ_ZERO_UNDEF()
DSelectionDAGDumper.cpp319 case ISD::CTTZ: return "cttz"; in getOperationName()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp125 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
126 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp294 setOperationAction(ISD::CTTZ , MVT::i8, Expand); in SPUTargetLowering()
295 setOperationAction(ISD::CTTZ , MVT::i16, Expand); in SPUTargetLowering()
296 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SPUTargetLowering()
297 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SPUTargetLowering()
298 setOperationAction(ISD::CTTZ , MVT::i128, Expand); in SPUTargetLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp118 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()

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