| /external/clang/tools/clang-format-vs/ |
| D | ClangFormat.sln | 4 …4F79EFBC}") = "ClangFormat", "ClangFormat\ClangFormat.csproj", "{7FD1783E-2D31-4D05-BF23-6EBE1B42B…
12 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
13 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Debug|Any CPU.Build.0 = Debug|Any CPU
14 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Release|Any CPU.ActiveCfg = Release|Any CPU
15 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Release|Any CPU.Build.0 = Release|Any CPU
|
| /external/libhevc/common/arm/ |
| D | ihevc_sao_band_offset_luma.s | 107 VDUP.8 D31,r11 @band_pos
125 … VADD.I8 D5,D1,D31 @band_table.val[0] = vadd_u8(band_table.val[0], band_pos)
128 … VADD.I8 D6,D2,D31 @band_table.val[1] = vadd_u8(band_table.val[1], band_pos)
131 … VADD.I8 D7,D3,D31 @band_table.val[2] = vadd_u8(band_table.val[2], band_pos)
134 … VADD.I8 D8,D4,D31 @band_table.val[3] = vadd_u8(band_table.val[3], band_pos)
207 VSUB.I8 D14,D13,D31 @vsub_u8(au1_cur_row, band_pos)
210 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
213 VSUB.I8 D18,D17,D31 @vsub_u8(au1_cur_row, band_pos)
216 VSUB.I8 D20,D19,D31 @vsub_u8(au1_cur_row, band_pos)
|
| D | ihevc_sao_band_offset_chroma.s | 119 VDUP.8 D31,r6 @band_pos_u
133 …VADD.I8 D5,D1,D31 @band_table_u.val[0] = vadd_u8(band_table_u.val[0], sao_ba…
136 …VADD.I8 D6,D2,D31 @band_table_u.val[1] = vadd_u8(band_table_u.val[1], sao_ba…
139 …VADD.I8 D7,D3,D31 @band_table_u.val[2] = vadd_u8(band_table_u.val[2], sao_ba…
142 …VADD.I8 D8,D4,D31 @band_table_u.val[3] = vadd_u8(band_table_u.val[3], sao_ba…
299 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
305 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
311 VSUB.I8 D19,D17,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
317 VSUB.I8 D23,D21,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
353 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
[all …]
|
| D | ihevc_sao_edge_offset_class1.s | 141 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
159 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
224 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
259 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
301 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
|
| D | ihevc_sao_edge_offset_class1_chroma.s | 145 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
163 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
236 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
276 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
318 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
|
| D | ihevc_resi_trans_32x32_a9q.s | 126 VLD1.S32 D31[0],[R9],R12
127 VLD1.S32 D31[1],[R9],R12 @ D31 - [16 0] [16 1] [24 0] [24 1]
129 VTRN.S32 D30,D31 @ D30 - [0 0] [0 1] [16 0] [16 1]
130 VTRN.S16 D30,D31 @ D31 - [8 0] [8 1] [24 0] [24 1]
131 VST1.S16 {D30,D31},[SP]
196 VADDW.S16 Q14,Q14,D31
331 VSWP D18,D31 @R1 transpose2
363 VST1.32 D31,[R2],R10 @ 1st cycle dual issued with MLAL
832 VLD1.S32 D31,[R9],R12 @ D31: [24 0] [24 1]
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 167 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
223 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
224 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
225 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
270 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
354 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
355 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
356 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_post_twiddle_overlap.s | 303 VUZP.16 D30, D31
319 VMLAL.S16 Q2, D31, D12
373 VMULL.S32 Q11, D31, D1
379 VMULL.S32 Q4, D31, D1
441 VUZP.16 D30, D31
559 VUZP.16 D30, D31
574 VMLAL.S16 Q2, D31, D12
630 VMULL.S32 Q11, D31, D1
638 VMULL.S32 Q4, D31, D1
704 VUZP.16 D30, D31
[all …]
|
| D | ia_xheaacd_mps_reoder_mulshift_acc.s | 225 VADD.I64 D31, D31, D24
|
| /external/harfbuzz_ng/test/shaping/data/in-house/tests/ |
| D | indic-old-spec.tests | 2 ../fonts/270b89df543a7e48e206a2d830c0e10e5265c630.ttf::U+0D38,U+0D4D,U+0D31,U+0D4D,U+0D31,U+0D4D:[g…
|
| /external/grpc-grpc/src/csharp/ |
| D | Grpc.sln | 26 …ng", "Grpc.IntegrationTesting\Grpc.IntegrationTesting.csproj", "{CB43BF5B-4D31-4347-A97A-0164B1248…
88 {CB43BF5B-4D31-4347-A97A-0164B1248B39}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
89 {CB43BF5B-4D31-4347-A97A-0164B1248B39}.Debug|Any CPU.Build.0 = Debug|Any CPU
90 {CB43BF5B-4D31-4347-A97A-0164B1248B39}.Release|Any CPU.ActiveCfg = Release|Any CPU
91 {CB43BF5B-4D31-4347-A97A-0164B1248B39}.Release|Any CPU.Build.0 = Release|Any CPU
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | isel-zext-vNi1.ll | 48 ; CHECK: r[[D31:([0-9]+:[0-9]+)]] = mask(p[[P30]])
49 ; CHECK: r1:0 = and(r[[D31]],r[[D30]])
|
| /external/swiftshader/third_party/LLVM/test/MC/MachO/ |
| D | x86_64-symbols.s | 98 D31: label
|
| D | x86_32-symbols.s | 98 D31: label
|
| /external/llvm/test/MC/MachO/ |
| D | x86_64-symbols.s | 98 D31: label
|
| D | x86_32-symbols.s | 98 D31: label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/MachO/ |
| D | x86_64-symbols.s | 98 D31: label
|
| D | x86_32-symbols.s | 98 D31: label
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 143 case AArch64::D31: return AArch64::B31; in getBRegFromDReg()
183 case AArch64::B31: return AArch64::D31; in getDRegFromBReg()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 67 case D31: case D30: case D29: case D28: in isARMArea3Register()
|
| D | ARMRegisterInfo.td | 134 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
155 def Q15 : ARMReg<15, "q15", [D30, D31]>;
293 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on
340 // Allocate starting at non-VFP2 registers D16-D31 first.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 80 case D31: case D30: case D29: case D28: in isARMArea3Register()
|
| D | ARMRegisterInfo.td | 146 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
167 def Q15 : ARMReg<15, "q15", [D30, D31]>;
334 // Allocate non-VFP2 registers D16-D31 first, and prefer even registers on
391 // Allocate starting at non-VFP2 registers D16-D31 first.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 143 case AArch64::D31: return AArch64::B31; in getBRegFromDReg()
183 case AArch64::B31: return AArch64::D31; in getDRegFromBReg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 127 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
150 def Q15 : ARMReg<15, "q15", [D30, D31]>;
277 // Allocate non-VFP2 registers D16-D31 first.
|