| /external/v8/src/arm64/ |
| D | constants-arm64.h | 763 DCPS1 = ExceptionFixed | 0x00A00001, enumerator
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| D | disasm-arm64.cc | 1289 case DCPS1: mnemonic = "dcps1"; form = "{'IDebug}"; break; in VisitException()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 746 DCPS1 = ExceptionFixed | 0x00A00001, enumerator
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| D | disasm-aarch64.cc | 2158 case DCPS1: in VisitException()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 1246 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| D | AArch64SchedKryoDetails.td | 478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1483 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1492 def : InstAlias<"dcps1", (DCPS1 0)>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1276 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1285 def : InstAlias<"dcps1", (DCPS1 0)>;
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| /external/capstone/arch/AArch64/ |
| D | AArch64GenAsmWriter.inc | 285 20524U, // DCPS1
2677 0U, // DCPS1
5230 // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC
7772 // (DCPS1 0)
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| D | AArch64GenDisassemblerTables.inc | 7211 /* 30177 */ MCD_OPC_Decode, 140, 2, 213, 1, // Opcode: DCPS1
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 699 UINT64_C(3567255553), // DCPS1
11883 case AArch64::DCPS1:
12751 0, // DCPS1 = 686
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| D | AArch64GenAsmWriter1.inc | 2447 147480U, // DCPS1
6966 0U, // DCPS1
10850 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC
14574 case AArch64::DCPS1:
14578 // (DCPS1 0)
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| D | AArch64GenAsmWriter.inc | 1498 73783U, // DCPS1
6017 0U, // DCPS1
9901 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC
13886 case AArch64::DCPS1:
13890 // (DCPS1 0)
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| D | AArch64GenAsmMatcher.inc | 12644 { 817 /* dcps1 */, AArch64::DCPS1, Convert__imm_95_0, 0, { }, },
12645 { 817 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
19113 { 817 /* dcps1 */, AArch64::DCPS1, Convert__imm_95_0, 0, { }, },
19114 { 817 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, 0, { MCK_Imm0_65535 }, },
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| D | AArch64GenInstrInfo.inc | 701 DCPS1 = 686,
6588 …UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #686 = DCPS1
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| D | AArch64GenDisassemblerTables.inc | 14066 /* 68766 */ MCD::OPC_Decode, 174, 5, 245, 2, // Opcode: DCPS1
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