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Searched refs:DefSU (Results 1 – 7 of 7) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp276 SUnit *DefSU = DefList[i]; in BuildSchedGraph() local
277 if (DefSU == &ExitSU) in BuildSchedGraph()
279 if (DefSU != SU && in BuildSchedGraph()
281 !DefSU->getInstr()->registerDefIsDead(Reg))) in BuildSchedGraph()
282 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); in BuildSchedGraph()
287 SUnit *DefSU = MemDefList[i]; in BuildSchedGraph() local
288 if (DefSU == &ExitSU) in BuildSchedGraph()
290 if (DefSU != SU && in BuildSchedGraph()
292 !DefSU->getInstr()->registerDefIsDead(*Alias))) in BuildSchedGraph()
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias)); in BuildSchedGraph()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp292 SUnit *DefSU = I->SU; in addPhysRegDeps() local
293 if (DefSU == &ExitSU) in addPhysRegDeps()
295 if (DefSU != SU && in addPhysRegDeps()
297 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
299 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
303 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
304 DefSU->addPred(Dep); in addPhysRegDeps()
445 SUnit *DefSU = V2SU.SU; in addVRegDefDeps() local
451 if (DefSU == SU) in addVRegDefDeps()
455 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
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DMachineScheduler.cpp1336 const SUnit *DefSU = getSUnit(DefMI); in computeCyclicCriticalPath() local
1337 if (!DefSU) in computeCyclicCriticalPath()
1340 unsigned LiveOutHeight = DefSU->getHeight(); in computeCyclicCriticalPath()
1341 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency; in computeCyclicCriticalPath()
1361 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency; in computeCyclicCriticalPath()
1368 LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" in computeCyclicCriticalPath()
DMachinePipeliner.cpp1264 SUnit *DefSU = getSUnit(DefMI); in changeDependences() local
1265 if (!DefSU) in changeDependences()
1282 if (P->getSUnit() == DefSU) in changeDependences()
3870 SUnit *DefSU = Insts.at(MoveDef); in orderDependence() local
3880 orderDependence(SSD, DefSU, Insts); in orderDependence()
3896 SUnit *DefSU = SSD->getSUnit(&Phi); in isLoopCarried() local
3897 unsigned DefCycle = cycleScheduled(DefSU); in isLoopCarried()
3898 int DefStage = stageScheduled(DefSU); in isLoopCarried()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp342 SUnit *DefSU = I->SU; in addPhysRegDeps() local
343 if (DefSU == &ExitSU) in addPhysRegDeps()
345 if (DefSU != SU && in addPhysRegDeps()
347 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
349 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
354 DefSU->addPred(Dep); in addPhysRegDeps()
496 SUnit *DefSU = V2SU.SU; in addVRegDefDeps() local
502 if (DefSU == SU) in addVRegDefDeps()
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
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DMachineScheduler.cpp1219 const SUnit *DefSU = getSUnit(DefMI); in computeCyclicCriticalPath() local
1220 if (!DefSU) in computeCyclicCriticalPath()
1223 unsigned LiveOutHeight = DefSU->getHeight(); in computeCyclicCriticalPath()
1224 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency; in computeCyclicCriticalPath()
1244 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency; in computeCyclicCriticalPath()
1251 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU(" in computeCyclicCriticalPath()
DMachinePipeliner.cpp1174 SUnit *DefSU = getSUnit(DefMI); in changeDependences() local
1175 if (!DefSU) in changeDependences()
1192 if (P->getSUnit() == DefSU) in changeDependences()
3737 SUnit *DefSU = Insts.at(MoveDef); in orderDependence() local
3747 orderDependence(SSD, DefSU, Insts); in orderDependence()
3753 orderDependence(SSD, DefSU, Insts); in orderDependence()
3770 SUnit *DefSU = SSD->getSUnit(&Phi); in isLoopCarried() local
3771 unsigned DefCycle = cycleScheduled(DefSU); in isLoopCarried()
3772 int DefStage = stageScheduled(DefSU); in isLoopCarried()