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Searched refs:DstReg (Results 1 – 25 of 240) sorted by relevance

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/external/mesa3d/src/mesa/program/
Dprogramopt.c90 newInst[i].DstReg.File = PROGRAM_OUTPUT; in insert_mvp_dp4_code()
91 newInst[i].DstReg.Index = VARYING_SLOT_POS; in insert_mvp_dp4_code()
92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in insert_mvp_dp4_code()
161 newInst[0].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
162 newInst[0].DstReg.Index = hposTemp; in insert_mvp_mad_code()
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
173 newInst[i].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
174 newInst[i].DstReg.Index = hposTemp; in insert_mvp_mad_code()
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
188 newInst[3].DstReg.File = PROGRAM_OUTPUT; in insert_mvp_mad_code()
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Dprog_optimize.c79 channel_mask = inst->DstReg.WriteMask & dst_mask; in get_src_arg_mask()
123 const GLuint mask = mov->DstReg.WriteMask; in get_dst_mask_for_mov()
224 if (inst->DstReg.File == file) { in replace_regs()
225 const GLuint index = inst->DstReg.Index; in replace_regs()
227 inst->DstReg.Index = map[index]; in replace_regs()
288 if (inst->DstReg.File == PROGRAM_TEMPORARY) { in _mesa_remove_dead_code_global()
289 assert(inst->DstReg.Index < REG_ALLOCATE_MAX_PROGRAM_TEMPS); in _mesa_remove_dead_code_global()
291 if (inst->DstReg.RelAddr) { in _mesa_remove_dead_code_global()
304 if (numDst != 0 && inst->DstReg.File == PROGRAM_TEMPORARY) { in _mesa_remove_dead_code_global()
305 GLint chan, index = inst->DstReg.Index; in _mesa_remove_dead_code_global()
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Dprog_instruction.c53 inst[i].DstReg.File = PROGRAM_UNDEFINED; in _mesa_init_instructions()
54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_init_instructions()
210 if (inst->DstReg.WriteMask == WRITEMASK_X || in _mesa_check_soa_dependencies()
211 inst->DstReg.WriteMask == WRITEMASK_Y || in _mesa_check_soa_dependencies()
212 inst->DstReg.WriteMask == WRITEMASK_Z || in _mesa_check_soa_dependencies()
213 inst->DstReg.WriteMask == WRITEMASK_W || in _mesa_check_soa_dependencies()
214 inst->DstReg.WriteMask == 0x0) { in _mesa_check_soa_dependencies()
221 if (inst->SrcReg[i].File == inst->DstReg.File && in _mesa_check_soa_dependencies()
222 inst->SrcReg[i].Index == inst->DstReg.Index) { in _mesa_check_soa_dependencies()
226 if (inst->DstReg.WriteMask & (1 << chan)) { in _mesa_check_soa_dependencies()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_tex.c68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in scale_texcoords()
69 inst_mov->U.I.DstReg.Index = temp; in scale_texcoords()
90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
91 inst_rcp->U.I.DstReg.Index = temp; in projective_divide()
92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
165 struct rc_dst_register output_reg = inst->U.I.DstReg; in radeonTransformTEX()
171 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX()
172 inst->U.I.DstReg.Index = tmp_texsample; in radeonTransformTEX()
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Dradeon_program_alu.c45 struct rc_dst_register DstReg, struct rc_src_register SrcReg) in emit1() argument
54 fpi->U.I.DstReg = DstReg; in emit1()
62 struct rc_dst_register DstReg, in emit2() argument
72 fpi->U.I.DstReg = DstReg; in emit2()
81 struct rc_dst_register DstReg, in emit3() argument
92 fpi->U.I.DstReg = DstReg; in emit3()
204 if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY) in is_dst_safe_to_reuse()
209 inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index) in is_dst_safe_to_reuse()
222 tmp = inst->U.I.DstReg.Index; in try_to_reuse_dst()
226 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
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Dr3xx_vertprog.c194 t_dst_index(vp, &vpi->DstReg), in ei_vector1()
195 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector1()
196 t_dst_class(vpi->DstReg.File), in ei_vector1()
211 t_dst_index(vp, &vpi->DstReg), in ei_vector2()
212 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector2()
213 t_dst_class(vpi->DstReg.File), in ei_vector2()
228 t_dst_index(vp, &vpi->DstReg), in ei_math1()
229 t_dst_mask(vpi->DstReg.WriteMask), in ei_math1()
230 t_dst_class(vpi->DstReg.File), in ei_math1()
246 t_dst_index(vp, &vpi->DstReg), in ei_lit()
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Dradeon_compiler.c130 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) in rc_calculate_inputs_outputs()
131 c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index; in rc_calculate_inputs_outputs()
182 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { in rc_move_output()
183 inst->U.I.DstReg.Index = new_output; in rc_move_output()
184 inst->U.I.DstReg.WriteMask &= writemask; in rc_move_output()
205 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { in rc_copy_output()
206 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_copy_output()
207 inst->U.I.DstReg.Index = tempreg; in rc_copy_output()
214 inst->U.I.DstReg.File = RC_FILE_OUTPUT; in rc_copy_output()
215 inst->U.I.DstReg.Index = output; in rc_copy_output()
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Dradeon_emulate_branches.c76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in handle_if()
77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C); in handle_if()
78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; in handle_if()
166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in allocate_and_insert_proxies()
167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index; in allocate_and_insert_proxies()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
185 inst_cmp->U.I.DstReg.File = file; in inject_cmp()
186 inst_cmp->U.I.DstReg.Index = index; in inject_cmp()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
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Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
275 inst->DstReg.WriteMask); in set_pair_instruction()
284 if (inst->DstReg.File == RC_FILE_OUTPUT) { in set_pair_instruction()
285 if (inst->DstReg.Index == c->OutputDepth) { in set_pair_instruction()
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
289 if (inst->DstReg.Index == c->OutputColor[i]) { in set_pair_instruction()
293 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
295 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
302 pair->RGB.DestIndex = inst->DstReg.Index; in set_pair_instruction()
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Dradeon_vert_fc.c130 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_bgnloop()
150 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_bgnloop()
164 inst->U.I.DstReg.Pred = RC_PRED_INV; in lower_brk()
170 inst->U.I.DstReg.Pred = RC_PRED_SET; in lower_brk()
173 build_pred_dst(&inst->U.I.DstReg, fc_state); in lower_brk()
184 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_endloop()
213 inst->U.I.DstReg.Pred = RC_PRED_SET; in lower_if()
229 build_pred_dst(&inst->U.I.DstReg, fc_state); in lower_if()
272 build_pred_dst(&inst->U.I.DstReg, &fc_state); in rc_vert_fc()
284 build_pred_dst(&inst->U.I.DstReg, &fc_state); in rc_vert_fc()
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp126 unsigned DstReg; in runOnMachineFunction() local
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; in runOnMachineFunction()
134 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
155 unsigned DstReg; in runOnMachineFunction() local
158 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; in runOnMachineFunction()
160 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
163 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
183 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp108 const unsigned DstReg,
121 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
124 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
233 unsigned DstReg = I.getOperand(0).getReg(); in selectCopy() local
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
241 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { in selectCopy()
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
278 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
296 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
189 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
193 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
207 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
209 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
228 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
230 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
238 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
240 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
248 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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DHexagonMCCompound.cpp84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
100 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
114 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
126 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
128 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
136 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
139 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup()
145 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp186 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
197 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
201 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
215 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
217 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
236 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
238 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
246 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
248 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
256 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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DHexagonMCCompound.cpp82 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
98 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
101 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
112 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
114 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
124 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
126 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
134 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
137 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup()
143 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp68 unsigned DstReg) { in buildMI() argument
69 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
144 unsigned DstReg = MI.getOperand(0).getReg(); in expandArith() local
151 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
177 unsigned DstReg = MI.getOperand(0).getReg(); in expandLogic() local
184 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
224 unsigned DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
231 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
276 unsigned DstReg = MI.getOperand(0).getReg(); in expand() local
280 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp140 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
143 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
148 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
161 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
163 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
178 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
180 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
189 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
192 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
197 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp312 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
315 MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i], in narrowScalar()
318 DstRegs.push_back(DstReg); in narrowScalar()
321 unsigned DstReg = MI.getOperand(0).getReg(); in narrowScalar() local
322 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
433 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
434 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset); in narrowScalar()
435 DstRegs.push_back(DstReg); in narrowScalar()
462 unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy); in narrowScalar() local
475 MIRBuilder.buildLoad(DstReg, SrcReg, *SplitMMO); in narrowScalar()
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/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp142 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
145 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
150 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
163 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
165 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
180 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
182 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
191 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
199 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTwoAddressInstructionPass.cpp130 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
136 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
393 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg() argument
396 DstReg = 0; in isCopyToReg()
398 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
401 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
407 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); in isCopyToReg()
442 unsigned SrcReg, DstReg; in isKilled() local
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
453 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { in isTwoAddrUse() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h42 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
46 Builder.buildAnyExtOrTrunc(DstReg, SrcReg); in tryCombineAnyExt()
60 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineZExt() local
61 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
74 Builder.buildAnd(DstReg, SrcCopyOrTrunc, MaskCstMIB); in tryCombineZExt()
88 unsigned DstReg = MI.getOperand(0).getReg(); in tryCombineSExt() local
89 LLT DstTy = MRI.getType(DstReg); in tryCombineSExt()
105 Builder.buildInstr(TargetOpcode::G_ASHR, DstReg, ShlMIB, SizeDiffMIB); in tryCombineSExt()
122 unsigned DstReg = MI.getOperand(0).getReg(); in tryFoldImplicitDef() local
123 LLT DstTy = MRI.getType(DstReg); in tryFoldImplicitDef()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp139 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
140 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
143 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
209 unsigned DstReg = MI.getOperand( in runOnMachineFunction() local
239 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
243 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
244 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
245 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
265 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp163 const unsigned DstReg = MI.getOperand(0).getReg(); in tryToreplicateChunks() local
179 .addReg(DstReg, in tryToreplicateChunks()
181 .addReg(DstReg) in tryToreplicateChunks()
204 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks()
205 .addReg(DstReg) in tryToreplicateChunks()
345 const unsigned DstReg = MI.getOperand(0).getReg(); in trySequenceOfOnes() local
352 .addReg(DstReg, in trySequenceOfOnes()
354 .addReg(DstReg) in trySequenceOfOnes()
369 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in trySequenceOfOnes()
370 .addReg(DstReg) in trySequenceOfOnes()
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DAArch64RedundantCopyElimination.cpp187 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
196 SrcReg != DstReg) { in knownRegValInBlock()
210 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
215 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
219 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
253 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
254 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
259 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
264 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()

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