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Searched refs:FMUL (Results 1 – 25 of 180) sorted by relevance

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/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DFMUL.java26 public class FMUL extends ArithmeticInstruction { class
30 public FMUL() { in FMUL() method in FMUL
31 super(org.apache.bcel.Const.FMUL); in FMUL()
DInstructionConst.java98 public static final ArithmeticInstruction FMUL = new FMUL(); field in InstructionConst
229 INSTRUCTIONS[Const.FMUL] = FMUL;
DInstructionConstants.java99 ArithmeticInstruction FMUL = new FMUL(); field
234 INSTRUCTIONS[Const.FMUL] = FMUL; in Clinit()
DArithmeticInstruction.java61 case Const.FMUL: in getType()
DVisitor.java270 void visitFMUL( FMUL obj ); in visitFMUL()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-fmul.mir16 ; CHECK: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY2]]
32 ; CHECK: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
49 ; CHECK: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY2]]
65 ; CHECK: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
Dlegalize-fmul.mir21 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-fmul-scalar.mir41 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[TRUNC]], [[TRUNC1]]
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s32)
80 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[TRUNC]], [[TRUNC1]]
81 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FMUL]](s64)
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dblend_jit.cpp229 src[swizComp] = FADD(FMUL(src[swizComp], VIMMED1(factor)), VIMMED1(0.5f)); in Quantize()
231 src[swizComp] = FMUL(src[swizComp], VIMMED1(1.0f /factor)); in Quantize()
247 srcBlend[i] = FMUL(src[i], srcFactor[i]); in BlendFunc()
248 dstBlend[i] = FMUL(dst[i], dstFactor[i]); in BlendFunc()
457 Value* pAlphaU8 = FMUL(pAlpha, VIMMED1(256.0f)); in AlphaTest()
588 currentSampleMask = FMUL(pClampedSrc, VBROADCAST(C((float)bits))); in Create()
703 FMUL(src[i], VIMMED1(scale[i])), in Create()
706 FMUL(dst[i], VIMMED1(scale[i])), in Create()
711 FMUL(src[i], VIMMED1(scale[i])), in Create()
714 FMUL(dst[i], VIMMED1(scale[i])), in Create()
[all …]
Dfetch_jit.cpp521 …vec = FMUL(vec, ConstantVector::get(std::vector<Constant*>(4, ConstantFP::get(mFP32Ty, 1.0 / 255.0… in JitLoadVertices()
525 …vec = FMUL(vec, ConstantVector::get(std::vector<Constant*>(4, ConstantFP::get(mFP32Ty, 1.0 / 65535… in JitLoadVertices()
537 …vec = FMUL(vec, ConstantVector::get(std::vector<Constant*>(4, ConstantFP::get(mFP32Ty, 1.0 / 128.0… in JitLoadVertices()
541 …vec = FMUL(vec, ConstantVector::get(std::vector<Constant*>(4, ConstantFP::get(mFP32Ty, 1.0 / 32768… in JitLoadVertices()
596 … vec = FMUL(SI_TO_FP(vec, VectorType::get(mFP32Ty, 4)), VBROADCAST(C(1/65536.0f))); in JitLoadVertices()
851 texels[compIndex] = FMUL(texels[compIndex], vScale); in ConvertFormat()
875 texels[compIndex] = FMUL(texels[compIndex], vScale); in ConvertFormat()
1694 … pGather = FMUL(SI_TO_FP(pGather, mSimd16FP32Ty), VBROADCAST_16(C(1 / 65536.0f))); in JitGatherVertices()
1715 … pGather = FMUL(SI_TO_FP(pGather, mSimdFP32Ty), VBROADCAST(C(1/65536.0f))); in JitGatherVertices()
2013 temp_lo = FMUL(CAST(fpCast, temp_lo, mSimdFP32Ty), conversionFactor); in Shuffle8bpcGatherd16()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp3627 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, in visitExp()
3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3651 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3670 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3674 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3677 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in visitExp()
3699 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in visitExp()
3703 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in visitExp()
3706 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in visitExp()
3709 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in visitExp()
[all …]
DLegalizeVectorOps.cpp148 case ISD::FMUL: in LegalizeOp()
331 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); in ExpandUINT_TO_FLOAT()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-irtranslator-fmuladd.ll23 ; FPOFF: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
24 ; FPOFF: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
/external/mesa3d/src/gallium/drivers/swr/
Dswr_shader.cpp930 Value *dist = FADD(FMUL(unwrap(cx), bpx), in CompileVS()
931 FADD(FMUL(unwrap(cy), bpy), in CompileVS()
932 FADD(FMUL(unwrap(cz), bpz), in CompileVS()
933 FMUL(unwrap(cw), bpw)))); in CompileVS()
1133 ff = FSUB(FMUL(ff, C(2.0f)), C(1.0f)); in CompileFS()
1241 vc = FMUL(vk, vc); in CompileFS()
1243 Value *interp = FMUL(va, vi); in CompileFS()
1244 Value *interp1 = FMUL(vb, vj); in CompileFS()
1249 interp = FMUL(interp, vw); in CompileFS()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp4181 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4185 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4197 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4201 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4204 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4225 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4228 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in getLimitedPrecisionExp2()
4231 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); in getLimitedPrecisionExp2()
[all …]
DDAGCombiner.cpp628 case ISD::FMUL: in isNegatibleForFree()
698 case ISD::FMUL: in GetNegatedExpression()
1406 case ISD::FMUL: return visitFMUL(N); in visit()
7795 if (Aggressive && N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7796 N1.getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7802 if (N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7810 if (N1.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7821 if (N00.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7833 if (N10.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7846 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp4418 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4422 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4438 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4441 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, in getLimitedPrecisionExp2()
4459 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); in getLimitedPrecisionExp2()
4462 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); in getLimitedPrecisionExp2()
4465 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); in getLimitedPrecisionExp2()
4468 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); in getLimitedPrecisionExp2()
[all …]
DDAGCombiner.cpp730 case ISD::FMUL: in isNegatibleForFree()
791 case ISD::FMUL: in GetNegatedExpression()
1561 case ISD::FMUL: return visitFMUL(N); in visit()
1881 BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || in foldBinOpIntoSelect()
10155 if (N.getOpcode() != ISD::FMUL) in visitFADDForFMACombine()
10213 N0.getOperand(2).getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
10226 N1.getOperand(2).getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
10367 if (N.getOpcode() != ISD::FMUL) in visitFSUBForFMACombine()
10626 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMADistributiveCombine()
10710 if (N.getOpcode() != ISD::FMUL) in isFMulNegTwo()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h235 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.h219 M_ALU2(FMUL)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h260 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp200 { ISD::FMUL, MVT::f64, 2 }, // mulsd in getArithmeticInstrCost()
201 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd in getArithmeticInstrCost()
202 { ISD::FMUL, MVT::v4f32, 2 }, // mulps in getArithmeticInstrCost()
492 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
496 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
637 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
638 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
700 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
701 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
702 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp166 case ISD::FMUL: in getArithmeticInstrCost()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h812 X86_INTRINSIC_DATA(avx512_mask_mul_pd_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
813 X86_INTRINSIC_DATA(avx512_mask_mul_pd_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
814 X86_INTRINSIC_DATA(avx512_mask_mul_pd_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
816 X86_INTRINSIC_DATA(avx512_mask_mul_ps_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
817 X86_INTRINSIC_DATA(avx512_mask_mul_ps_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
818 X86_INTRINSIC_DATA(avx512_mask_mul_ps_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
820 X86_INTRINSIC_DATA(avx512_mask_mul_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FMUL,
822 X86_INTRINSIC_DATA(avx512_mask_mul_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FMUL,

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