Searched refs:FMULS (Results 1 – 23 of 23) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SPARC/ |
| D | disable-fsmuld-fmuls.ll | 2 …lc %s -march=sparc -mattr=no-fmuls -o - | FileCheck --check-prefix=CHECK --check-prefix=NO-FMULS %s
13 ; NO-FMULS: fsmuld
14 ; NO-FMULS: fdtos
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| /external/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 61 "LEON3 erratum fix: Replace FMULS instruction with a "
63 "to replace FMULS">;
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| D | LeonPasses.cpp | 258 if (Opcode == SP::FMULS && MI.getNumOperands() == 3) { in runOnMachineFunction()
861 case SP::FMULS: in runOnMachineFunction()
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| D | SparcInstrInfo.td | 1235 // FMULS generates an erratum on LEON processors, so by disabling this instruction
1238 def FMULS : F3_3<2, 0b110100, 0b001001001,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 151 #define FMULS (OPC1(0x2) | OPC3(0x34) | DOP(0x49)) macro
1160 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FMULS, FMULD) | FD(dst_r) | FS1(src1) | FS2(src2), MOVA… in sljit_emit_fop2()
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| D | sljitNativePPC_common.c | 179 #define FMULS (HI(59) | LO(25)) macro
1736 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FMULS, FMUL) | FD(dst_r) | FA(src1) | FC(src2) /* FMUL … in sljit_emit_fop2()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRInstrFormats.td | 281 // 0b10 for FMULS
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| D | AVRInstrInfo.td | 570 def FMULS : FFMULRdRr<0b10,
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| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrFormats.td | 279 // 0b10 for FMULS
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| D | AVRInstrInfo.td | 536 def FMULS : FFMULRdRr<0b10,
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 657 def FMULS : F3_3<2, 0b110100, 0b001001001,
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| /external/v8/src/ppc/ |
| D | constants-ppc.h | 1856 V(fmuls, FMULS, 0xEC000032) \
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 206 case PPC::FMULS: in isAssociativeAndCommutative()
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| D | PPCInstrInfo.td | 2608 defm FMULS : AForm_3r<59, 25,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 428 FMULS,
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| D | PPCInstrInfo.cpp | 242 case PPC::FMULS: in isAssociativeAndCommutative()
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| D | PPCInstrInfo.td | 2888 defm FMULS : AForm_3r<59, 25,
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| /external/capstone/arch/Sparc/ |
| D | SparcGenDisassemblerTables.inc | 620 /* 2385 */ MCD_OPC_Decode, 222, 1, 26, // Opcode: FMULS
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| D | SparcGenAsmWriter.inc | 243 5714U, // FMULS
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1307 def FMULS : AForm_3<59, 25,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 1242 def FMULS : F3_3<2, 0b110100, 0b001001001,
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenDisassemblerTables.inc | 1510 /* 6232 */ MCD_OPC_Decode, 129, 4, 90, // Opcode: FMULS
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| D | PPCGenAsmWriter.inc | 533 22041U, // FMULS
1806 0U, // FMULS
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