Searched refs:FPRRegBankID (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 42 createRegisterBank(AArch64::FPRRegBankID, "FPR"); in AArch64RegisterBankInfo()
45 addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
94 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
143 getRegBank(AArch64::FPRRegBankID)); in getInstrAlternativeMappings()
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| D | AArch64RegisterBankInfo.h | 26 FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q. enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
312 getCopyMapping(AArch64::FPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
317 getCopyMapping(AArch64::FPRRegBankID, AArch64::GPRRegBankID, Size), in getInstrAlternativeMappings()
322 getCopyMapping(AArch64::GPRRegBankID, AArch64::FPRRegBankID, Size), in getInstrAlternativeMappings()
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| D | AArch64InstructionSelector.cpp | 155 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
252 case AArch64::FPRRegBankID: in selectBinaryOp()
309 case AArch64::FPRRegBankID: in selectLoadStoreUIOp()
380 assert((DstSize <= 64 || RegBank.getID() == AArch64::FPRRegBankID) && in selectCopy()
821 if (RB.getID() != AArch64::FPRRegBankID) { in select()
1198 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterBank.inc | 14 FPRRegBankID,
80 RegisterBank FPRRegBank(/* ID */ ARM::FPRRegBankID, /* Name */ "FPRB", /* Size */ 128, /* CoveredRe…
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMRegisterBankInfo.cpp | 61 checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) && in checkPartialMappings()
64 checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) && in checkPartialMappings()
192 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
434 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| D | ARMInstructionSelector.cpp | 129 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
132 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
178 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
219 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
268 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
753 if (SrcRegBank.getID() == ARM::FPRRegBankID) { in select()
865 ARM::FPRRegBankID, Size); in select()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterBank.inc | 15 FPRRegBankID,
112 RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* Size */ 512, /* Covere…
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