| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CmovConversion.cpp | 721 unsigned FalseReg = in convertCmovInstsToBranches() local
726 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
729 FalseReg = FRIt->second; in convertCmovInstsToBranches()
731 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
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| D | X86InstrInfo.h | 347 unsigned FalseReg) const override;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 507 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
509 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
533 FalseReg.setImplicit(); in optimizeSelect()
534 NewMI.add(FalseReg); in optimizeSelect()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 509 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
511 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
535 FalseReg.setImplicit(); in optimizeSelect()
536 NewMI.addOperand(FalseReg); in optimizeSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 745 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
758 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
784 unsigned FalseReg) const { in insertSelect()
791 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
844 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2205 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2212 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2214 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2216 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
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| D | PPCInstrInfo.h | 241 unsigned FalseReg) const override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 244 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
249 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
291 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg) in LowerFPToInt()
298 .addReg(FalseReg) in LowerFPToInt()
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| D | WebAssemblyFastISel.cpp | 865 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
866 if (FalseReg == 0) in selectSelect()
870 std::swap(TrueReg, FalseReg); in selectSelect()
905 .addReg(FalseReg) in selectSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 264 unsigned TrueReg, unsigned FalseReg,
271 unsigned TrueReg, unsigned FalseReg) const override;
276 unsigned TrueReg, unsigned FalseReg) const;
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| D | SIInstrInfo.cpp | 684 unsigned FalseReg) const { in insertVectorSelect()
694 .addReg(FalseReg) in insertVectorSelect()
706 .addReg(FalseReg) in insertVectorSelect()
717 .addReg(FalseReg) in insertVectorSelect()
729 .addReg(FalseReg) in insertVectorSelect()
742 .addReg(FalseReg) in insertVectorSelect()
755 .addReg(FalseReg) in insertVectorSelect()
769 .addReg(FalseReg) in insertVectorSelect()
1786 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
1794 assert(MRI.getRegClass(FalseReg) == RC); in canInsertSelect()
[all …]
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 728 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
729 if (FalseReg == 0) in selectSelect()
733 std::swap(TrueReg, FalseReg); in selectSelect()
764 .addReg(FalseReg) in selectSelect()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 182 unsigned FalseReg) const override;
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| D | PPCInstrInfo.cpp | 687 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
729 unsigned FalseReg) const { in insertSelect()
739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
792 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 159 unsigned FalseReg) const override;
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| D | AArch64InstrInfo.cpp | 368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, in canInsertSelect() argument
373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
389 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
411 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
519 TrueReg = FalseReg; in insertSelect()
521 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
525 FalseReg = NewVReg; in insertSelect()
534 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 636 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
648 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
672 unsigned FalseReg) const { in insertSelect()
690 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
692 FalseReg = FReg; in insertSelect()
700 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
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| D | SystemZInstrInfo.h | 219 unsigned FalseReg) const override;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 640 auto FalseReg = MIB->getOperand(3).getReg(); in selectSelect() local
642 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
647 .addUse(FalseReg) in selectSelect()
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| D | ARMBaseInstrInfo.cpp | 2101 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2103 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2133 FalseReg.setImplicit(); in optimizeSelect()
2134 NewMI.add(FalseReg); in optimizeSelect()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 690 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
714 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 759 unsigned FalseReg, int &CondCycles, in canInsertSelect() argument
782 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 189 unsigned FalseReg) const override;
|
| D | AArch64InstrInfo.cpp | 488 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
494 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
510 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
532 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
640 TrueReg = FalseReg; in insertSelect()
642 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
646 FalseReg = NewVReg; in insertSelect()
655 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
660 .addReg(FalseReg) in insertSelect()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 328 unsigned FalseReg) const override;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1900 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
1902 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1932 FalseReg.setImplicit(); in optimizeSelect()
1933 NewMI.addOperand(FalseReg); in optimizeSelect()
|