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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrFMA.td10 // This file describes FMA (Fused Multiply-Add) instructions.
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
45 // Fused Multiply-Add
55 // Fused Negative Multiply-Add
/external/tensorflow/tensorflow/contrib/remote_fused_graph/
DREADME.md1 # Remote Fused Graph
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td192 // Fused multiply-add.
198 // Fused multiply-subtract.
212 // Fused multiply-add (unnormalized).
DSystemZInstrFP.td473 // Fused multiply-add.
480 // Fused multiply-subtract.
DSystemZOperators.td663 // Fused multiply-subtract, using the natural operand order.
667 // Fused multiply-add and multiply-subtract, but with the order of the
DSystemZInstrInfo.td101 // Fused compare-and-branch instructions.
208 // Fused compare-and-trap instructions.
292 // Fused compare and conditional sibling calls.
312 // Fused compare and conditional returns.
/external/virglrenderer/docs/
DGL-status.txt22 - Fused multiply-add
/external/llvm/lib/Target/X86/
DX86InstrFMA.td10 // This file describes FMA (Fused Multiply-Add) instructions.
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
91 // Fused Multiply-Add
118 // Fused Negative Multiply-Add
263 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
DX86Schedule.td72 defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
DX86.td147 "Enable AVX-512 Integer Fused Multiple-Add",
/external/llvm/lib/Target/ARM/
DARMScheduleV6.td246 // Single-precision Fused FP MAC
249 // Double-precision Fused FP MAC
DARMScheduleA8.td330 // Single-precision Fused FP MAC
334 // Double-precision Fused FP MAC
878 // Double-register Fused FP Multiple-Accumulate
882 // Quad-register Fused FP Multiple-Accumulate
DARMScheduleA9.td616 // Single-precision Fused FP MAC
624 // Double-precision Fused FP MAC
1729 // Double-register Fused FP Multiple-Accumulate
1738 // Quad-register Fused FP Multiple-Accumulate
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleV6.td246 // Single-precision Fused FP MAC
249 // Double-precision Fused FP MAC
DARMScheduleA8.td330 // Single-precision Fused FP MAC
334 // Double-precision Fused FP MAC
878 // Double-register Fused FP Multiple-Accumulate
882 // Quad-register Fused FP Multiple-Accumulate
DARMScheduleA9.td616 // Single-precision Fused FP MAC
624 // Double-precision Fused FP MAC
1729 // Double-register Fused FP Multiple-Accumulate
1738 // Quad-register Fused FP Multiple-Accumulate
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTX.td28 "Disable Fused-Multiply Add">;
/external/tensorflow/tensorflow/contrib/fused_conv/
DBUILD2 # A Fused Conv Bias Activation operator wrapper.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFMA.td10 // This file describes FMA (Fused Multiply-Add) instructions.
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
123 // Fused Multiply-Add
154 // Fused Negative Multiply-Add
385 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
DX86Schedule.td238 defm WriteFMA : X86SchedWritePair; // Fused Multiply Add.
239 defm WriteFMAX : X86SchedWritePair; // Fused Multiply Add (XMM).
240 defm WriteFMAY : X86SchedWritePair; // Fused Multiply Add (YMM).
241 defm WriteFMAZ : X86SchedWritePair; // Fused Multiply Add (ZMM).
DX86SchedBroadwell.td260 defm : BWWriteResPair<WriteFMA, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
261 defm : BWWriteResPair<WriteFMAX, [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
262 defm : BWWriteResPair<WriteFMAY, [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td415 // Fused multiply-add.
422 // Fused multiply-subtract.
DSystemZOperators.td562 // Fused multiply-subtract, using the natural operand order.
566 // Fused multiply-add and multiply-subtract, but with the order of the
/external/llvm/docs/
DCompileCudaWithLLVM.rst173 Fused multiply-add instructions can be much faster than the unfused
/external/mesa3d/docs/
Dfeatures.txt119 - Fused multiply-add DONE ()

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