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Searched refs:GPR_32 (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86GenRegisterBankInfo.def58 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
DX86CallingConv.td31 list<Register> GPR_32 = [];
44 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
64 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
71 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
89 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
167 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td836 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
837 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
860 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
863 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
866 def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
DMipsInstrInfo.td229 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
2185 GPR_32 {
2190 GPR_32 {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td950 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
951 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
991 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
994 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
997 def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
DMipsInstrInfo.td261 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
2649 GPR_32, ISA_MIPS1;
2652 GPR_32, ISA_MIPS1;
2697 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>, ISA_MIPS1, GPR_32;
2699 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>, ISA_MIPS1, GPR_32;
2701 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>, ISA_MIPS1, GPR_32;
2703 defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>, ISA_MIPS1, GPR_32;
2705 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>, ISA_MIPS1, GPR_32;
2840 def NORImm : NORIMM_DESC_BASE<GPR32Opnd, simm32_relaxed>, GPR_32;
2842 simm32_relaxed:$imm)>, GPR_32;
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp1863 static const unsigned GPR_32[] = { // 32-bit registers. in LowerFormalArguments_Darwin() local
1879 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); in LowerFormalArguments_Darwin()
1885 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
3123 static const unsigned GPR_32[] = { // 32-bit registers. in LowerCall_Darwin() local
3137 const unsigned NumGPRs = array_lengthof(GPR_32); in LowerCall_Darwin()
3141 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp3565 static const MCPhysReg GPR_32[] = { // 32-bit registers. in LowerFormalArguments_Darwin() local
3578 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); in LowerFormalArguments_Darwin()
3584 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
5732 static const MCPhysReg GPR_32[] = { // 32-bit registers. in LowerCall_Darwin() local
5744 const unsigned NumGPRs = array_lengthof(GPR_32); in LowerCall_Darwin()
5748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp4046 static const MCPhysReg GPR_32[] = { // 32-bit registers. in LowerFormalArguments_Darwin() local
4059 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); in LowerFormalArguments_Darwin()
4065 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerFormalArguments_Darwin()
6289 static const MCPhysReg GPR_32[] = { // 32-bit registers. in LowerCall_Darwin() local
6301 const unsigned NumGPRs = array_lengthof(GPR_32); in LowerCall_Darwin()
6305 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32; in LowerCall_Darwin()