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Searched refs:HasV7Ops (Results 1 – 25 of 26) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARM.td116 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
203 [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
206 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
209 [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
213 def : ProcNoItin<"cortex-m3", [HasV7Ops,
218 def : ProcNoItin<"cortex-m4", [HasV7Ops,
DARMSubtarget.h46 bool HasV7Ops; variable
193 bool hasV7Ops() const { return HasV7Ops; } in hasV7Ops()
DARMSubtarget.cpp47 , HasV7Ops(false) in ARMSubtarget()
DARMInstrInfo.td181 AssemblerPredicate<"HasV7Ops">;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSystemRegister.inc278 { "basepri", 0x811, 0x111, 0x811, {ARM::HasV7Ops} }, // 24
279 { "basepri_max", 0x812, 0x112, 0x812, {ARM::HasV7Ops} }, // 25
280 { "faultmask", 0x813, 0x113, 0x813, {ARM::HasV7Ops} }, // 26
287 { "basepri_ns", 0x891, 0x191, 0x891, {ARM::Feature8MSecExt, ARM::HasV7Ops} }, // 33
288 { "faultmask_ns", 0x893, 0x193, 0x893, {ARM::Feature8MSecExt, ARM::HasV7Ops} }, // 34
DARMGenSubtargetInfo.inc126 HasV7Ops = 110,
212 …{ "armv7-a", "ARMv7a architecture", { ARM::ARMv7a }, { ARM::HasV7Ops, ARM::FeatureNEON, ARM::Featu…
213 …{ "armv7-m", "ARMv7m architecture", { ARM::ARMv7m }, { ARM::HasV7Ops, ARM::FeatureThumb2, ARM::Fea…
214 …{ "armv7-r", "ARMv7r architecture", { ARM::ARMv7r }, { ARM::HasV7Ops, ARM::FeatureDB, ARM::Feature…
215 …{ "armv7e-m", "ARMv7em architecture", { ARM::ARMv7em }, { ARM::HasV7Ops, ARM::FeatureThumb2, ARM::…
218 …{ "armv7ve", "ARMv7ve architecture", { ARM::ARMv7ve }, { ARM::HasV7Ops, ARM::FeatureNEON, ARM::Fea…
305 …{ "v7", "Support ARM v7 instructions", { ARM::HasV7Ops }, { ARM::HasV6T2Ops, ARM::FeaturePerfMon, …
307 …{ "v8", "Support ARM v8 instructions", { ARM::HasV8Ops }, { ARM::HasV7Ops, ARM::FeatureAcquireRele…
313 …8m.main", "Support ARM v8M Mainline instructions", { ARM::HasV8MMainlineOps }, { ARM::HasV7Ops } },
16605 if (Bits[ARM::HasV7Ops]) HasV7Ops = true;
DARMGenDisassemblerTables.inc11241 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV7Ops]);
11243 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV7Ops] && Bits[ARM::FeatureMP]);
11319 return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && Bits[ARM::HasV7Ops]);
11323 …return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && Bits[ARM::HasV7Ops] && Bits[ARM::Featu…
DARMGenMCCodeEmitter.inc11201 if ((FB[ARM::HasV7Ops]))
/external/llvm/lib/Target/ARM/
DARM.td292 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
298 [HasV7Ops, FeatureAcquireRelease]>;
307 [HasV7Ops]>;
408 def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
414 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
420 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
427 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
DARMSubtarget.h94 bool HasV7Ops = false; variable
400 bool hasV7Ops() const { return HasV7Ops; } in hasV7Ops()
DARMInstrInfo.td213 AssemblerPredicate<"HasV7Ops", "armv7">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARM.td413 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
421 [HasV7Ops]>;
425 [HasV7Ops, FeatureAcquireRelease]>;
560 def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
566 def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops,
575 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
581 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
589 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
DARMSystemRegister.td80 let Requires = [{ {ARM::HasV7Ops} }] in {
100 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
DARMSubtarget.h150 bool HasV7Ops = false; variable
526 bool hasV7Ops() const { return HasV7Ops; } in hasV7Ops()
DARMInstrInfo.td245 AssemblerPredicate<"HasV7Ops", "armv7">;
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp36 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp39 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
DARMTargetStreamer.cpp130 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3367 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadShift()
3454 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm8()
3535 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm12()
3652 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadLabel()
4149 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
4177 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3367 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadShift()
3455 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm8()
3536 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadImm12()
3653 bool hasV7Ops = featureBits[ARM::HasV7Ops]; in DecodeT2LoadLabel()
4150 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
4179 if (!(FeatureBits[ARM::HasV7Ops])) { in DecodeMSRMask()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp821 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp820 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp118 return STI.getFeatureBits() & ARM::HasV7Ops; in hasV7Ops()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp273 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp466 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()

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